Sydney Riley
20fec0177d
Corrected authorship for IFU.S tests file
2023-03-29 15:20:46 -07:00
Sydney Riley
b0237eaa8b
Starting IFU tests including c.fld compressed instruction
2023-03-29 15:15:47 -07:00
Kip Macsai-Goren
491ef14b71
Resolved ImperasDV receiving incorrect cause values
2023-03-29 15:04:56 -07:00
Noah Limpert
6acf1dadda
instantiate 5 4KiB arrays, aim to thrash all 4 ways
2023-03-29 13:08:33 -07:00
Noah Limpert
1e07460d0e
access of 4KiB spaced mem locations, aim to fill + evict a line of all 4 ways
2023-03-29 13:07:34 -07:00
Alec Vercruysse
d507f85190
icache coverage improvements by simplifying logic
2023-03-29 13:04:00 -07:00
Ross Thompson
5c4b753a1e
Merge pull request #173 from davidharrishmc/dev
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Test improvements including FPU coverage
2023-03-29 13:00:25 -05:00
David Harris
9d8f9e4428
Reduced number of bits in mcause and medeleg registers
2023-03-29 07:02:09 -07:00
David Harris
59f825a54b
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-29 06:19:10 -07:00
David Harris
d604a4fd33
Merge pull request #171 from AlecVercruysse/fix_152
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add check for legal funct3 for IW instructions
2023-03-29 06:18:31 -07:00
David Harris
d059da6eca
Turned on FS bit in fpu.S coverage test
2023-03-29 06:10:05 -07:00
Limnanthes Serafini
91fe85486c
Log file cleanup
2023-03-29 04:12:10 -07:00
Limnanthes Serafini
0ab06f08c4
Log file cleanup
2023-03-29 04:11:54 -07:00
Limnanthes Serafini
a4d4f0b914
Log file cleanup
2023-03-29 04:11:43 -07:00
Limnanthes Serafini
abf9da3c8b
Git issues, repushing
2023-03-29 04:10:47 -07:00
Limnanthes Serafini
7f2ce66a85
A first pass at the Cache simulator.
2023-03-29 04:03:55 -07:00
Diego Herrera Vicioso
36d7ddf501
Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs.
2023-03-28 22:48:17 -07:00
David Harris
115c042015
Turned off hpm counters
2023-03-28 21:28:56 -07:00
David Harris
f2c24b869d
Simplified fctrl
2023-03-28 21:13:48 -07:00
David Harris
3dc1c6673d
Started adding fpu fctrl tests
2023-03-28 21:13:25 -07:00
Alec Vercruysse
46df428e56
add check for legal funct3 for IW instructions
2023-03-28 15:59:48 -07:00
David Harris
92a7e86942
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:33:18 -07:00
David Harris
16742cbcb6
Merge pull request #170 from ross144/main
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Fixed issue 148 and problems with i/d cache address loggers.
2023-03-28 14:32:54 -07:00
Ross Thompson
d0f8db7939
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-28 16:31:50 -05:00
Ross Thompson
84860a062d
Modified the testbench to not use the loggers for unsupported configurations.
2023-03-28 16:27:54 -05:00
David Harris
6849eeae0c
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:27:08 -07:00
Ross Thompson
d33f4cfdef
Merge branch 'main' of github.com:ross144/cvw
2023-03-28 16:22:26 -05:00
Ross Thompson
c65c9e52d4
Disable loggers by default.
2023-03-28 16:20:45 -05:00
Ross Thompson
650a1a8d7e
Now reports if there is a hit or miss.
2023-03-28 16:20:14 -05:00
Ross Thompson
ef26600689
Restored performance counter reports.
2023-03-28 16:15:05 -05:00
Ross Thompson
a5601ea264
Now have logging of i/d cache addresses, but the performance counter reports are x's.
2023-03-28 16:09:54 -05:00
Ross Thompson
65d83b6f63
Merge branch 'main' of github.com:ross144/cvw
2023-03-28 14:47:16 -05:00
Ross Thompson
366a96a0fc
Possible fix for issue 148.
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I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Kevin Kim
582c561cb1
comment formatting
2023-03-28 11:40:19 -07:00
Kevin Kim
926f3d2a5a
Merge branch 'openhwgroup:main' into bitmanip_cleanup
2023-03-28 11:31:18 -07:00
David Harris
64bf9510ad
Added support (untested) for half and quad conversions
2023-03-28 10:53:06 -07:00
David Harris
36a0d35ae5
fixed fp->fp conversions
2023-03-28 10:35:41 -07:00
David Harris
4e50cc3379
support more fp -> fp conversions
2023-03-28 10:28:01 -07:00
David Harris
074fd1d9c3
Fixed fmv decoder
2023-03-28 10:21:33 -07:00
Ross Thompson
e49cf8a028
Merge pull request #169 from davidharrishmc/dev
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PMP Fix to issue 132
2023-03-28 11:49:00 -05:00
David Harris
2c8fcc24e0
Fixed bitrot in testfloat tests
2023-03-28 09:35:19 -07:00
David Harris
2427e43ffd
Moved rv32 peripheral tests using TEST-LIB to wally32priv because rv32imc doesn't support PMP
2023-03-28 09:08:48 -07:00
David Harris
2e5c50e24a
Fixed RV32 tests after PMP fix
2023-03-28 08:35:23 -07:00
David Harris
e8904411ce
Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
2023-03-28 06:58:17 -07:00
David Harris
4594dffc7f
Set PMP to allow all user/supervisor accesses in WALLY-init-lib
2023-03-28 06:46:11 -07:00
David Harris
f24a9be4dc
Merge pull request #168 from AlecVercruysse/makecoverage
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Add tests/coverage/ tests as a target to sim/Makefile
2023-03-28 05:23:04 -07:00
David Harris
cce4d06f53
Merge pull request #167 from ross144/main
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Added clarificaiton to buildroot linux testvector generation
2023-03-28 05:21:44 -07:00
David Harris
2e238c15aa
CSRS privileged coverage test
2023-03-28 04:37:56 -07:00
Ross Thompson
514738ad96
Now reports i cache and d cache memory accesses.
2023-03-27 23:44:50 -05:00
Ross Thompson
03666dab1c
Merge pull request #166 from magpyed/patch-1
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Fixing order of local repo commands in README
2023-03-27 22:41:20 -05:00
