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Author	SHA1	Message	Date
David Harris	b09fd0d0a8	Simplified tlbmixer mux to and-or	2021-07-08 23:34:24 -04:00
David Harris	4d53a935b3	Fixed missing stall in InstrRet counter	2021-07-08 20:08:04 -04:00
David Harris	230654ea76	Eliminate reserved bits from TLB RAM	2021-07-08 17:35:00 -04:00
David Harris	f806707cb0	Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram	2021-07-08 16:58:11 -04:00
David Harris	b1592a0542	TLB cleanup to match diagrams	2021-07-08 16:52:06 -04:00
David Harris	dc44ca4b0b	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-07 06:32:29 -04:00
David Harris	6dc49dd073	Renamed tlb ReadLines to Matches	2021-07-07 06:32:26 -04:00
Abe	09a092abd5	Updated MISA defining as well as porting sizes for peripherals (34 to 56)	2021-07-07 02:37:09 -04:00
Abe	ed3c06b851	Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time.	2021-07-07 02:28:11 -04:00
Abe	ab61590f77	Removed debugging loop to test timers for clarity	2021-07-06 23:37:43 -04:00
Abe	63e4db1158	Updated portme file to include counters MTIME and MINSTRET. Timer currently set to read milliseconds running at 100MHZ, but this can be changed by setting a different clock speed in the testbench sv file and manipulating TIMER_RES_DIVIDER on line 120	2021-07-06 23:35:47 -04:00
Abe	244e197348	Changed SvMode to SVMode on line 76	2021-07-06 23:28:58 -04:00
David Harris	1301f4df7f	Added ASID matching for CAM	2021-07-06 18:56:25 -04:00
Kip Macsai-Goren	1652e09b38	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-06 18:54:41 -04:00
David Harris	2b26bbbbd7	more TLB name touchups	2021-07-06 18:39:30 -04:00
Kip Macsai-Goren	8dfa28125f	fixed upper bits page fault signal	2021-07-06 18:32:47 -04:00
David Harris	73024fee2d	connected signals in tlb by name instead of .*	2021-07-06 17:22:10 -04:00
David Harris	18f4fa600a	changed tlbphysicalpagemask to structural	2021-07-06 17:16:58 -04:00
David Harris	404ba5988a	changed tlbphysicalpagemask to structural	2021-07-06 17:08:04 -04:00
David Harris	eb948f81dc	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-06 15:29:49 -04:00
David Harris	78850bfcd8	MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB	2021-07-06 15:29:42 -04:00
Kip Macsai-Goren	794becd886	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-06 15:05:51 -04:00
Ross Thompson	dc4c26d2a2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-06 13:45:20 -05:00
Ross Thompson	d85bf23af3	Merged several of the load/store/instruction access faults inside the mmu. ... Still need to figure out what is wrong with the generation of load page fault when dtlb hit.	2021-07-06 13:43:53 -05:00
bbracker	0e708a72f3	more completely uncomment MMU tests to make sim wally work	2021-07-06 14:33:52 -04:00
Kip Macsai-Goren	61fc9bb266	edited tests so regression would pass with float enabled. this IS NOT a comprehensive test for fs yet	2021-07-06 14:28:26 -04:00
Abe	79e62b7c53	Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140)	2021-07-06 12:37:58 -04:00
Ross Thompson	61f870809d	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-06 10:41:45 -05:00
Ross Thompson	71a23626d5	Fixed bug in the LSU pagetable walker interlock.	2021-07-06 10:41:36 -05:00
David Harris	6d25ea1508	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-06 10:44:17 -04:00
David Harris	4c2cbe3200	Cleaned up tlb output muxing	2021-07-06 10:44:05 -04:00
David Harris	087bed3b67	Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines	2021-07-06 10:38:30 -04:00
Kip Macsai-Goren	35f89f9e99	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-06 10:16:34 -04:00
David Harris	69c0358ffd	Created tlbcontrol module to hide details	2021-07-06 03:25:11 -04:00
David Harris	6785ed9994	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
David Harris	3cb9e5acd3	Fixed adrdecs to use Access signals for TIMs	2021-07-05 23:42:58 -04:00
David Harris	a390736f26	Don't generate HPTW when MEM_VIRTMEM=0	2021-07-05 23:35:44 -04:00
David Harris	e3f6758265	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-05 23:23:17 -04:00
David Harris	8ca7abaa02	Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0	2021-07-05 20:35:31 -04:00
Ross Thompson	4d9b87a823	Fixed combo loop in the page table walker.	2021-07-05 16:37:26 -05:00
Ross Thompson	59913e13aa	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-05 16:07:27 -05:00
Kip Macsai-Goren	770420b448	added new mmu tests to makefrag and commented out in the testbench	2021-07-05 10:54:30 -04:00
Kip Macsai-Goren	331ee30881	added final mmu test that passes make. They still don't pass simulation.	2021-07-05 10:49:23 -04:00
Kip Macsai-Goren	8dc1f28a9c	cleaned up comments, minor edits	2021-07-05 10:47:20 -04:00
Kip Macsai-Goren	61ab9de347	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-05 10:45:44 -04:00
David Harris	e65fb5bb35	Added F_SUPPORTED flag to disable floating point unit when not in MISA	2021-07-05 10:30:46 -04:00
David Harris	b8b7fab02b	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
David Harris	bbbc1d2f89	Simplified PLIC with generate	2021-07-04 19:17:15 -04:00
David Harris	ce3edd0288	Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb	2021-07-04 19:02:56 -04:00
David Harris	39fa84efdd	Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb	2021-07-04 18:56:30 -04:00