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Configurable RISC-V Processor
1,212 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
0e708a72f3
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bbracker 0e708a72f3 more completely uncomment MMU tests to make sim wally work
2021-07-06 14:33:52 -04:00
riscv-coremark
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
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.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md

README.md

riscv-wally

Configurable RISC-V Processor