Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-26 06:25:20 +00:00
Code Issues Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
1,237 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.3%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
b09fd0d0a8
Go to file
David Harris b09fd0d0a8 Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
riscv-coremark Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time. 2021-07-07 02:28:11 -04:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined Simplified tlbmixer mux to and-or 2021-07-08 23:34:24 -04:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore split intermediate GDB output file into smaller files for better debug experience 2021-06-26 07:18:26 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor