Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-27 23:14:27 +00:00
Code Issues Packages Projects Releases Wiki Activity
1,237 Commits 4 Branches 2 Tags 52 MiB
b09fd0d0a8
Commit Graph

1237 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
bbracker
f394b91515 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 17:37:49 -04:00
bbracker
f84a689c19 fixed PCtext error by using blocking assignments 2021-06-18 17:37:40 -04:00
Kip Macsai-Goren
2117162a47 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 13:27:10 -04:00
Ross Thompson
0250d52ae3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-18 12:24:42 -05:00
Ross Thompson
22ea801edb Improved some names in icache. 2021-06-18 12:22:41 -05:00
Ross Thompson
d4de8a54a2 Icache now uses physical lenght bits rather than XLEN. 2021-06-18 12:02:59 -05:00
David Harris
43bc17350b Restored wally-busybear testbench now that graphical sim is working 2021-06-18 12:36:25 -04:00
bbracker
958f60c704 restore graphical buildroot sim 2021-06-18 11:58:16 -04:00
Abe
892c14430b Updated directory coremark_bare's wally-config file to define PMP_ENTRIES 2021-06-18 11:46:25 -04:00
Kip Macsai-Goren
a47519df27 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 10:46:43 -04:00
bbracker
1e93bbd119 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 09:49:37 -04:00
bbracker
72f1e3eab6 buildroot added to regression because it passes regression 2021-06-18 09:49:30 -04:00
David Harris
21a55458ca Made MemPAdrM and related signals PA_BITS wide 2021-06-18 09:36:22 -04:00
David Harris
a3f3533cce Changed physical addresses to PA_BITS in size in MMU and TLB 2021-06-18 09:11:31 -04:00
bbracker
0980ce92bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 08:15:40 -04:00
bbracker
8ae333a6b2 remove unused testbench-busybear.sv 2021-06-18 08:15:19 -04:00
David Harris
cc78504ae4 Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX 2021-06-18 08:13:15 -04:00
David Harris
72d8d34e3c allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
e03912f64c Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
David Harris
8357b14957 Further cleaning of PMA checker 2021-06-17 22:27:39 -04:00
Kip Macsai-Goren
dd256acf53 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-17 21:41:15 -04:00
David Harris
91a13999a9 Added SUPPORTED to each peripheral in each config file 2021-06-17 21:36:32 -04:00
David Harris
54d9147c12 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-17 18:54:46 -04:00
David Harris
5e7ed4bd88 added inputs to pmaadrdec 2021-06-17 18:54:39 -04:00
David Harris
09c5e27853 Started simplifying PMA checker 2021-06-17 16:28:06 -04:00
Abe
985b08c7d1 Commit message 2021-06-17 14:49:13 -04:00
Kip Macsai-Goren
f16742bfe4 removed old page table, test data read not working 2021-06-17 13:48:16 -04:00
Kip Macsai-Goren
39bc39f691 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-17 12:17:13 -04:00
bbracker
076469230f added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version 2021-06-17 12:09:10 -04:00
bbracker
db0abfd36d enable TIME CSR for 32 bit mode as well 2021-06-17 11:34:16 -04:00
bbracker
7d1469a06c provide time and timeh CSRs based on CLINT's counter 2021-06-17 08:38:30 -04:00
bbracker
832e4fc7e3 making linux waveforms more useful 2021-06-17 08:37:37 -04:00
bbracker
0647094e73 PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable 2021-06-17 05:19:36 -04:00
bbracker
e93e528aa1 changed parsedCSRs2] to parsedCSRs 2021-06-17 05:18:14 -04:00
bbracker
902fd85e9c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-17 00:50:14 -04:00
bbracker
7de660f8aa still not sure if QEMU workaround is correct, but here is all linux progress so far 2021-06-17 00:50:02 -04:00
Kip Macsai-Goren
7464e60926 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-16 17:37:40 -04:00
bbracker
7a652139b5 mcause test fixes and s-mode interrupt bugfix 2021-06-16 17:37:08 -04:00
bbracker
3f6b018f66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-16 16:17:53 -04:00
bracker
d1bab12e1e chmod +x'd privileged testgen scripts 2021-06-16 10:28:57 -05:00
bbracker
8d8d2aabc2 fixed incorrect expectation fof CLINT spec 2021-06-15 19:24:24 -04:00
Kip Macsai-Goren
420befebdb removed example page table file. no longer needed. 2021-06-15 18:14:01 -04:00
David Harris
b69992872e Added page tables to MMU tests 2021-06-15 17:54:13 -04:00
Kip Macsai-Goren
e9977b1702 added page table example file, continued work on mmu test 2021-06-15 16:13:37 -04:00
David Harris
1d8c5683a3 Started WALLY-MMU 2021-06-15 11:52:16 -04:00
bbracker
2f53adf557 whoops forgot RV32 2021-06-15 11:33:01 -04:00
bbracker
cda9a1d8e6 apply changes to privileged tests 2021-06-15 11:32:10 -04:00
bbracker
6f1f585c2c Merge remote-tracking branch 'origin/fixPrivTests' into main 2021-06-15 09:57:46 -04:00
Katherine Parry
920ff984ca Updated FMA 2021-06-14 13:42:53 -04:00
David Harris
5e01f71c52 disabled Verilator WIDTH warnings in ICCacheCntrl 2021-06-12 19:50:06 -04:00