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afe66d0ee4
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61 Commits

Author SHA1 Message Date
David Harris
afe66d0ee4 Added prefetch instructions; sent cbo instructions to LSU 2023-07-02 10:55:35 -07:00
David Harris
723b8266cb Added prefetch signals 2023-07-02 10:06:58 -07:00
David Harris
482e4e6e92 Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions 2023-07-02 09:35:05 -07:00
David Harris
b6ae5661b4 Added environment configuration control (menvcfg/senvcfg) of cbo instructions 2023-07-02 01:52:25 -07:00
David Harris
15314a9c9a Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations 2023-07-02 00:34:30 -07:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
David Harris
9e839988dc Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
d3aebc00d4 Fixed UART merge conflict 2023-06-15 11:36:37 -07:00
Harshini Srinath
dd7c13cc2d Update wallypipelinedsoc.sv 
Program clean up
 2023-06-15 10:39:37 -07:00
Harshini Srinath
b4469fd3bf Update wallypipelinedcore.sv 
Program clean up
 2023-06-15 10:38:38 -07:00
Harshini Srinath
85a513e542 Update cvw.sv 
Program clean up
 2023-06-15 10:29:33 -07:00
David Harris
430537a052 Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this. 2023-06-14 09:44:52 -07:00
Ross Thompson
ee4352975c This parameterizes the testbench but does not use the verilator updates or the new testbench. 2023-06-12 11:00:30 -05:00
Ross Thompson
e27dfb8ce0 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
Ross Thompson
c7536663c0 Merge pull request #319 from davidharrishmc/dev 
Renamed Performance Counter extension
 2023-06-09 21:21:45 -04:00
David Harris
b70b0c7c5e Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare 2023-06-09 14:40:01 -07:00
David Harris
df96900aa1 Added named support for Zicntr and Zihpm 2023-06-09 09:35:51 -07:00
Ross Thompson
a8a8422557 Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger. 2023-06-09 09:28:24 -05:00
Ross Thompson
1ceea51d8b Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
Ross Thompson
a963f0af3a Updated source code to be compatible with verilator 5.011 for lint only. 2023-05-31 10:44:23 -05:00
Ross Thompson
1315a0bf4a Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check. 2023-05-26 16:00:14 -05:00
Ross Thompson
b517a96261 Update top level parameterized. Simulation slowed down to 4.5 minutes. 2023-05-26 12:13:11 -05:00
Ross Thompson
8cf38b28aa The privileged unit is parameterized using Lim's method. 2023-05-26 12:03:46 -05:00
Ross Thompson
02a788a083 PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue. 2023-05-26 11:06:48 -05:00
Ross Thompson
fcb1c63f5f Partial parameterization into mmu. 2023-05-24 16:12:41 -05:00
Ross Thompson
5f5f33787d MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue. 2023-05-24 15:01:35 -05:00
Ross Thompson
1299319d0b More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done. 2023-05-24 14:56:02 -05:00
Ross Thompson
b91b54589e Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down. 2023-05-24 14:05:44 -05:00
Ross Thompson
930fb67308 Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
Ross Thompson
da9cf02ba0 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 14:55:12 -05:00
Ross Thompson
394f2d65f2 Progress on bug 203. 2023-04-05 13:20:04 -05:00
David Harris
4552f9cf8c Fixed WFI to commit when an interrupt occurs 2023-04-04 09:32:26 -07:00
Ross Thompson
0afba56927 Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
Ross Thompson
46b1bca4fc Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
David Harris
e03a533775 Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault 2023-03-22 06:29:30 -07:00
David Harris
a1eccf37dc Fix Issue 145 2023-03-22 04:33:14 -07:00
David Harris
6922298f21 Replaced FenceM with InvalidateICacheM for event counting of fence.i 2023-03-18 09:24:31 -07:00
Ross Thompson
31fcc0daf7 Renamed PCFSpill to PCSpillF. 2023-03-06 17:50:57 -06:00
Ross Thompson
0cb5369351 Renamed BTB misprediction to BTA. 2023-03-03 00:18:34 -06:00
Ross Thompson
5b5677ccb8 Added divide cycle counter. 2023-03-02 23:59:52 -06:00
Ross Thompson
aabb454d1c Added the i and d cache cycle counters. 2023-03-02 23:54:56 -06:00
Ross Thompson
cfca77172e Added fence counter. 2023-03-02 23:29:20 -06:00
Ross Thompson
a313b10912 Added store stall to performance counters. 2023-03-02 23:10:54 -06:00
Ross Thompson
b98e007a53 Cleaned up branch predictor performance counters. 2023-03-01 17:05:42 -06:00
Ross Thompson
a6917d07f3 Name cleanup. 2023-02-28 17:48:58 -06:00
Ross Thompson
2ebe600f54 Name changes to reflect diagrams. 2023-02-28 15:37:25 -06:00
Ross Thompson
bc5aecf948 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-27 09:48:03 -06:00
David Harris
cf8b5f0783 Added support for ZMMUL 2023-02-27 07:29:53 -08:00