67 Commits

Author	SHA1	Message	Date
James Stine	8b4c3920db	Update Appendix D + wrapped memories	2023-01-28 19:46:43 -06:00
David Harris	5df4679bcb	Removed old link to imperas-riscv-tests	2023-01-26 14:53:25 -08:00
James Stine	a5d402c6ce	This adds the Dockerfile for those who might be interested in building a docker container for Wally	2023-01-23 17:29:58 -06:00
David Harris	1ec62606f9	sram1p1rw cleanup	2022-12-20 02:57:51 -08:00
Ross Thompson	fc05e27416	Updated riscv arch test removed misaligned1.	2022-12-04 00:18:10 +00:00
David Harris	f326b18af6	embench cleaned up	2022-09-08 11:38:01 -07:00
Katherine Parry	655e2d3810	merged radix-2 sqrt into divider - doesnt work yet	2022-07-23 00:41:18 +00:00
slmnemo	df568fd202	Added PLIC and UART tests and new functions to the test library	2022-07-22 07:10:39 -07:00
Daniel Torres	c29a60c198	changed gitignore, updated version of arch tests on main build	2022-07-21 21:10:15 -07:00
Katherine Parry	fbe8bb2298	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
Daniel Torres	e46e96e080	changed the default branch of embench	2022-07-21 10:14:05 -07:00
David Harris	e22d6a2f9a	Removed Sky130 libraries	2022-07-06 13:50:11 +00:00
Katherine Parry	03d823f5d7	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
Madeleine Masser-Frye	59a514ae81	remove run deletion with wally synthesis	2022-06-17 19:45:38 +00:00
DTowersM	7c0f4dd954	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-06-13 23:34:35 +00:00
DTowersM	39ed36d0ba	added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)	2022-06-13 23:23:57 +00:00
Katherine Parry	5f7072bd96	postprocessing unit created and passing all tests	2022-06-13 22:47:51 +00:00
Madeleine Masser-Frye	5a9f1a3970	update	2022-06-03 21:17:50 +00:00
Katherine Parry	559c0c278e	added unpackinput.sv	2022-05-31 16:18:50 +00:00
Madeleine Masser-Frye	d5e0eb9eb4	added optimized area plotting	2022-05-30 18:54:02 +00:00
Katherine Parry	835a4e4606	fixed lint error	2022-05-28 10:20:13 -07:00
Madeleine Masser-Frye	4ed7283ad1	fixed normalization vertical axes, added TechSpecs type	2022-05-28 04:57:18 +00:00
Katherine Parry	d5c249bf71	unpacker adds 1 to denorm expoents	2022-05-27 14:37:10 -07:00
Katherine Parry	3c63db9554	some optimizations in unpacker	2022-05-27 11:36:04 -07:00
cturek	0f1da722bf	Set up the divider for on-the-fly conversion	2022-05-26 16:45:28 +00:00
Katherine Parry	f4b9ade942	added fcvt.sv	2022-05-26 00:10:51 +00:00
cturek	650779318d	Fixed exponent verification, added sign module and added sign tests	2022-05-25 23:36:21 +00:00
Katherine Parry	c264585fe8	single and double conversions pass all tests	2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye	378523087f	added widths for csa in ppa	2022-05-22 23:23:02 +00:00
Katherine Parry	6bc31f2e78	Fixed unpacker bug LT EQ LE pass testfloat	2022-05-20 17:19:50 +00:00
Madeleine Masser-Frye	230aae000e	fixed dynamic energy units	2022-05-20 01:59:19 +00:00
Katherine Parry	cc0ab94ebc	Added fp tests - doesnpass yet	2022-05-19 16:32:30 +00:00
mmasserfrye	2675c217e0	cleaned lint for ppa.sv	2022-05-12 20:20:05 +00:00
David Harris	8372bc86a7	Removing unused signals	2022-05-12 14:36:15 +00:00
mmasserfrye	52b0e7d567	filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv	2022-05-12 07:22:06 +00:00
Ross Thompson	4d3fde3829	Updated wally to point to riscv-arch-test tag 2.7.3	2022-04-16 15:32:43 -05:00
Katherine Parry	c307cff503	fixed errors and warnings in rv32e	2022-04-07 17:21:20 +00:00
David Harris	049c55769a	fpu compare simplification, minor cleanup	2022-03-29 17:11:28 +00:00
Katherine Parry	2042374102	FMA parameterized and FMA testbench reworked	2022-03-19 19:39:03 +00:00
David Harris	eda60a7691	Moved Softfloat / TestFloat	2022-02-26 19:17:32 +00:00
James Stine	b9480a4643	Added the 12T submodule to the project.	2022-02-03 19:26:41 -06:00
David Harris	069f270d1a	Removed soc_flow	2022-01-31 22:58:33 +00:00
David Harris	2d112698b7	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
David Harris	c367d19fc6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-31 00:59:49 +00:00
David Harris	ea85e185f1	gitmodules	2022-01-31 00:59:44 +00:00
James Stine	ef811c7786	Remove book_flow to add back later - will add synthDC back within 30m	2022-01-28 08:18:30 -06:00
David Harris	384cd0d092	Added synthesis submodules	2022-01-27 14:31:34 +00:00
David Harris	1e533cdf25	Removed and restored embench-iot	2022-01-25 22:12:28 +00:00
David Harris	26013a984b	Fixed sumtest reference output; added embench benchmark directory	2022-01-24 23:21:09 +00:00
David Harris	de7b9c127e	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00