DTowersM 7c0f4dd954 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2022-06-13 23:34:35 +00:00
..
coremark@f3e8f2e094	added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)	2022-06-13 23:23:57 +00:00
embench-iot@261a65e0a2	cleaned lint for ppa.sv	2022-05-12 20:20:05 +00:00
riscv-arch-test@be67c99bd4	postprocessing unit created and passing all tests	2022-06-13 22:47:51 +00:00
riscv-dv@a7e27bc046	cleaned lint for ppa.sv	2022-05-12 20:20:05 +00:00
riscv-tests@cf04274f50	cleaned lint for ppa.sv	2022-05-12 20:20:05 +00:00
sky130_osu_sc_t12@f1eef84473	Added the 12T submodule to the project.	2022-02-03 19:26:41 -06:00
sky130_osu_sc_t18@83f5245e1a	Added synthesis submodules	2022-01-27 14:31:34 +00:00
SoftFloat-3e	unpacker adds 1 to denorm expoents	2022-05-27 14:37:10 -07:00
TestFloat-3e	Moved Softfloat / TestFloat	2022-02-26 19:17:32 +00:00
imperas-riscv-tests	Added partially working MMU tests	2021-12-29 03:14:16 +00:00