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202 Commits

Author SHA1 Message Date
Ross Thompson
63c9c3a1a8 Pushed vcu118 to 71MHz. 2023-08-25 17:04:50 -05:00
Jacob Pease
1ca8673c43 Added help option to the flash-sd script. 2023-08-22 13:37:33 -05:00
Jacob Pease
7c10de443d Merge branch 'main' of github.com:openhwgroup/cvw 2023-08-21 16:10:09 -05:00
David Harris
38e437c724
Merge pull request #383 from ross144/main 
Adds Zicbom support for D-cache only.  I-cache not yet supported.  Tests 32 and 64 bit versions.  Please rebuild regressions wally32 and wally64.  To save rebuild time edit lines 11-12 of tests/riscof/Makefile
 2023-08-21 13:32:00 -07:00
Ross Thompson
d855922bfa Removed unused file. 2023-08-21 15:12:59 -05:00
Ross Thompson
04b68696c6 Updated artyA7 debugger to match book. 2023-08-21 14:35:42 -05:00
Jacob Pease
3896998dab Added SPDX headers to other probe scripts. 2023-08-16 14:04:25 -05:00
Jacob Pease
48a8dc7738 Added SPDX header to probe script. 2023-08-16 13:05:37 -05:00
Jacob Pease
3477f177ac Fixed bug caused by errant tab size in probe script. 2023-08-16 12:20:08 -05:00
Jacob Pease
4cba4cb657 Added probe script to generate a single probe for the fpga. 2023-08-16 12:12:31 -05:00
Ross Thompson
087d418c35 Updateds to vcu118 constraints and device tree. 2023-08-02 16:51:32 -05:00
Ross Thompson
f35b05e608 Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails. 2023-08-02 16:14:04 -05:00
Ross Thompson
06c8c31682 Fixed constraint in VCU118. 2023-08-02 13:02:28 -05:00
Ross Thompson
49ee1ea62a Clean up vcu118 synth scripts. 2023-08-01 14:39:33 -05:00
Ross Thompson
1b237a14a1 Pushed performance of arty a7 to 23Mhz. 2023-07-31 14:13:09 -05:00
Jacob Pease
87a6ad5a87 Removed non-existent SDC dependency from VCU targets in FPGA Makefile. 2023-07-27 15:01:20 -05:00
Jacob Pease
8b97d323e0 Fixed GPIO pin names in fpgaTop.v 2023-07-25 20:57:04 -05:00
Ross Thompson
717833b11a Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
fd187e9ee6 Merge branch 'main' of github.com:ross144/cvw 2023-07-24 10:47:05 -05:00
Ross Thompson
d239b0649e Improved timing constraints for arty a7 to push clock speed to 20Mhz. 2023-07-24 10:46:49 -05:00
Ross Thompson
6099b0e763 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
6e17cfba03 At least it simulates and gets through fpga elaboration. 2023-07-21 18:40:26 -05:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
37078f3d9b Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
36785848a5 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
7873d26678 Fixed a bunch of timing constraints for the arty a7 board. 2023-07-19 17:08:16 -05:00
Ross Thompson
bae5359c6b Fixed typo in fpga top for arty a7. 2023-07-19 11:37:29 -05:00
Ross Thompson
2854452ecc Removed all old configuration files. 2023-07-19 10:28:54 -05:00
Ross Thompson
3bf2b35704 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
5ce4ac963f Updated arty a7 fpga top. 2023-07-17 15:55:57 -05:00
Jacob Pease
142ec857ed Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
Ross Thompson
4b3b590f21 Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits. 2023-06-22 12:55:49 -05:00
Ross Thompson
626a918668 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
25103176a0 Updated fpga wave config. 2023-06-19 12:28:30 -05:00
Ross Thompson
8242544efa Updated fpga wally wrapper to work with the ILA. 2023-06-19 12:15:48 -05:00
Ross Thompson
24b8c6c391 I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
Ross Thompson
4bee446cad Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
Ross Thompson
2f35bec970 FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
Jacob Pease
2ad9c72acc The Vivado-RISC-V SDC works. Wally is now booting through it. 2023-05-26 15:42:33 -05:00
Ross Thompson
86de36b6ce FPGA makefile update. 2023-04-25 16:24:26 -05:00
Ross Thompson
d513956bb9 Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 11:08:35 -05:00
Ross Thompson
a6903ac5f3 Yeah We boot linux on the arty a7! 2023-04-19 11:17:33 -05:00
Ross Thompson
c463bd8cdd Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram. 
but the data is wrong.
 2023-04-19 10:35:18 -05:00
Ross Thompson
d783456746 Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed. 2023-04-18 17:45:41 -05:00
Ross Thompson
bb4ebd9b61 More debug stuff. 2023-04-18 16:00:10 -05:00
Ross Thompson
667524efcb Added more signals to debugger in hopes I can figure out why the mig is not responding. 2023-04-18 15:51:52 -05:00
Jacob Pease
53de2bf782 AHB triggers write, but AXI side doesn't update. 2023-04-18 15:23:22 -05:00
Ross Thompson
2df6c6cb0f It's almost working. 2023-04-18 14:24:59 -05:00
Ross Thompson
ac95087042 Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. 2023-04-17 20:05:59 -05:00
Ross Thompson
dd7f5310e4 Fixed timing constraint issue. 2023-04-17 19:53:43 -05:00