Rose Thompson
b1a711ae0f
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
9404a339ee
Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
2024-07-23 17:44:37 -05:00
Rose Thompson
6c212ebf0e
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
e8e71ad643
Code cleanup.
2024-07-23 16:35:05 -05:00
Rose Thompson
57ea39d685
Fixed rvvi csr counting.
2024-07-23 16:22:23 -05:00
Rose Thompson
54e0289608
Fixed bugs in the rvvi synth logic which encoded csr instructions.
2024-07-23 16:16:11 -05:00
Rose Thompson
1eff86b7ae
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
2024-07-23 13:18:03 -05:00
Rose Thompson
c463201d68
Moved all rvvi files to rvvi directory.
2024-07-23 13:03:21 -05:00
Rose Thompson
825dbefcb2
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
2024-07-23 12:26:03 -05:00
Rose Thompson
bb74a0f96b
Resolved more lint errors in the rvvi synthesized hardware.
2024-07-23 12:23:04 -05:00
Rose Thompson
121342f4cc
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
2024-07-22 16:12:06 -05:00
Rose Thompson
00c30239bf
Cleaned up rvvisynth.sv
2024-07-22 12:22:41 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
a324e79b6f
Updated the ethernet frame gap for a faster computer.
2024-07-19 13:12:13 -05:00
Ross Thompson
f0096f5a43
Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11
Yay! the trigger is correctly working now!
2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8
Really close to having the trigger in module work.
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Can trigger on the data of the correct frame, but trigger in is still not
working.
2024-07-09 19:04:51 -05:00
Ross Thompson
612a281f62
Added module to receive ethernet frame and trigger the ila.
2024-06-26 11:05:31 -07:00
Ross Thompson
249d58244a
It's working!!!!!!
2024-06-20 15:48:30 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
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Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Ross Thompson
2581ea0b74
Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames.
2024-06-18 16:48:49 -07:00
Ross Thompson
00e0549c36
I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word.
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The default input interface to the interface is 8-bit and I used 32-bit. I suspect there is a bug in the implementation for non-8-bit interfaces.
2024-06-18 07:44:19 -07:00
Ross Thompson
cccb40e4b5
Got the tracer not overrunning ethernet buffers so frames are not being dropped.
2024-06-17 09:16:24 -07:00
Ross Thompson
47523c97ac
Getting closer to figuring out the lost ethernet frame bugs.
2024-06-13 15:46:54 -07:00
Rose Thompson
fc62f80407
Closer to fully working hardware tracer.
2024-06-04 11:31:05 -05:00
Rose Thompson
80f98b3223
now have a working ethernet daemon to collect frames and partially decode into RVVI.
2024-06-04 10:20:51 -05:00
Rose Thompson
dc904cdbbb
The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field.
2024-06-03 18:10:25 -05:00
Rose Thompson
a830bd57f0
Have to reverse the byte order for ethernet frame length.
2024-05-31 17:46:43 -05:00
Rose Thompson
e05ebc30b8
Almost worked out the bugs in packetizer.
2024-05-31 16:48:41 -05:00
Rose Thompson
0dccc6051d
draft of receiving code to unpack the ethernet frames into rvvi.
2024-05-31 13:55:25 -05:00
Rose Thompson
1df3e5239a
This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer.
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wireshark is able to capture the frames and they match the expected data!
2024-05-30 17:57:28 -05:00
Rose Thompson
ca90c6ba48
Added the ethernet files. These are part of another repo.
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We should remove before mainlining this.
2024-05-30 16:33:49 -05:00
Rose Thompson
9703055758
The FPGA is synthesizing with the rvvi and ethernet hardware.
2024-05-30 15:37:17 -05:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
d341974c5b
Have rvvi to ethernet working.
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Now it is time to move the hardware to the FPGA.
Ideally I don't want Wally to actually have any of this code since it's entirely
debug code so it will move to the fpga/src directory.
Then we'll need to add additional logic to the mmcm to generate the correct clocks.
Finally we'll update the I/O to add ethernet.
2024-05-24 15:52:13 -05:00
Rose Thompson
bf9f45d319
We have a simulation of the ethernet transmission working.
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This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
