cvw/src/rvvi
Ross Thompson cf986b5fb8 Really close to having the trigger in module work.
Can trigger on the data of the correct frame, but trigger in is still not
working.
2024-07-09 19:04:51 -05:00
..
axis_adapter.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
axis_async_fifo_adapter.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
axis_async_fifo.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
axis_gmii_rx.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
axis_gmii_tx.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
eth_axis_tx.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
eth_mac_1g.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
eth_mac_mii_fifo.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
eth_mac_mii.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
lfsr.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
mac_ctrl_rx.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
mac_ctrl_tx.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
mac_pause_ctrl_rx.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
mac_pause_ctrl_tx.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
mii_phy_if.sv Getting closer to figuring out the lost ethernet frame bugs. 2024-06-13 15:46:54 -07:00
packetizer.sv It's working!!!!!! 2024-06-20 15:48:30 -07:00
rvvisynth.sv Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames. 2024-06-18 16:48:49 -07:00
ssio_ddr_in.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
ssio_sdr_in.sv Added the ethernet files. These are part of another repo. 2024-05-30 16:33:49 -05:00
triggergen.sv Really close to having the trigger in module work. 2024-07-09 19:04:51 -05:00