David Harris
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a138ef37b1
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Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)
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2023-12-15 19:26:50 -08:00 |
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David Harris
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29f57958a9
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Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
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2023-12-14 15:32:36 -08:00 |
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David Harris
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166c98b6f6
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Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn
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2023-12-13 19:43:17 -08:00 |
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David Harris
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6c017141c5
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Renamed HADE to ADUE for Svadu
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2023-12-13 11:49:04 -08:00 |
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Rose Thompson
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9dfe421c55
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Yay! Zicclsm passes my regression test now.
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2023-11-10 18:28:51 -06:00 |
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Rose Thompson
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c0e02ae190
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Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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02ab9fe99c
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Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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bd866e1025
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Fixed some more bugs in the Zicclsm signature.
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2023-11-10 17:36:10 -06:00 |
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Rose Thompson
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efecb0c346
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Fixed bug in the Zicclsm test.
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2023-11-10 17:34:23 -06:00 |
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Rose Thompson
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ada354f443
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Fixed bug in the misaligned access test.
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2023-11-10 17:02:15 -06:00 |
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Rose Thompson
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b74bfbeefd
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
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naichewa
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d67badfc60
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fix hardware interlock, hold mode deassert
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2023-11-08 15:20:51 -08:00 |
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naichewa
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a5837eb62c
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
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naichewa
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4651b807ed
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added test cases
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2023-11-02 15:43:08 -07:00 |
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Rose Thompson
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0a4ed5515b
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Merge branch 'main' into Zicclsm
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2023-11-02 12:55:51 -05:00 |
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Rose Thompson
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afa1d85e3b
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Doesn't yet fully work.
Thomas is going to finish debugging while I'm on the RISCV summit next week.
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2023-11-02 12:07:42 -05:00 |
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Rose Thompson
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7ba891f607
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Progress. I think the remaining bugs are in the regression test's signature.
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2023-11-01 17:51:48 -05:00 |
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naichewa
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9aa8a7af3e
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comments, more test cases
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2023-11-01 01:26:34 -07:00 |
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Rose Thompson
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5660eff57d
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Working through issues with the psill logic.
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2023-10-31 18:50:13 -05:00 |
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Rose Thompson
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4984b3935f
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Progress
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2023-10-31 14:50:33 -05:00 |
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Rose Thompson
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5ca428d6a8
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Fixed bugs in misaligned test.
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2023-10-31 12:49:35 -05:00 |
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Rose Thompson
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c061440141
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First stab at the misaligned test.
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2023-10-31 12:30:10 -05:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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2330f4ee63
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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Rose Thompson
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2241976d29
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Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
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2023-10-30 18:26:11 -05:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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Rose Thompson
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0fd5b3b2ce
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Updated comments in the cboz tests.
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2023-10-20 15:15:47 -05:00 |
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Rose Thompson
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5a4028064a
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Updated comments for the cbom tests.
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2023-10-20 15:13:52 -05:00 |
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naichewa
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0ff9ce527d
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Merge branch 'main' into spi
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2023-10-16 22:59:50 -07:00 |
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David Harris
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ac4216b43d
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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David Harris
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6245748ed7
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Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
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2023-10-15 15:31:03 -07:00 |
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David Harris
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b4891d88db
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Added WALLY minfo test for rv32
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2023-10-15 06:48:22 -07:00 |
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David Harris
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434d6b2c5c
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minfo test working again with mconfigptr for RV64
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2023-10-15 06:41:52 -07:00 |
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naichewa
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aa5abfc8e8
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always working after reg bit swizzle changes
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2023-10-13 14:22:32 -07:00 |
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naichewa
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f231c3d3a3
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correct delay0, fmt register test entries
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2023-10-12 15:13:23 -07:00 |
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naichewa
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d5d4f9d044
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transferred spi changes in ECA-authorized commit
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2023-10-12 13:36:57 -07:00 |
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David Harris
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d526d28804
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Added MENVCFG.HADE bit and updated SVADU to depend on this bit
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2023-10-04 09:34:28 -07:00 |
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Ross Thompson
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12c3c98824
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Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.
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2023-08-30 11:29:44 -05:00 |
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David Harris
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8d3ff59673
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Completed basic tests of svnapot and svpbmt
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2023-08-28 06:57:35 -07:00 |
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Ross Thompson
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cd3349bd26
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Added rv32 cboz test.
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2023-08-24 17:02:53 -05:00 |
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Ross Thompson
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914b6f9734
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Now have CBOZ instructions working!
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2023-08-24 16:47:35 -05:00 |
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Ross Thompson
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7d51690b7c
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Oups forgot to include the 32-bit cbom test in previous commit.
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2023-08-24 09:04:41 -05:00 |
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Ross Thompson
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310b700550
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Have a working 32 bit cbom test!
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2023-08-21 13:46:09 -05:00 |
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Ross Thompson
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d4c6ba627d
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Working CBO tests for 64 bit!
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2023-08-21 12:55:07 -05:00 |
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Ross Thompson
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5ed096e4bc
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Made a bunch of progress towards getting cbo instructions tested.
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2023-08-21 11:46:21 -05:00 |
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David Harris
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c137a1c8cf
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Fixed timer interrupt testing
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2023-06-09 17:20:41 -07:00 |
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David Harris
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f68b9c224a
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Fixed WALLY-trap test case to use menvcfg
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2023-06-09 15:24:26 -07:00 |
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David Harris
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b70b0c7c5e
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Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
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2023-06-09 14:40:01 -07:00 |
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David Harris
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19096a812a
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Added Zifencei ISA to tests where necessary to support new compiler
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2023-05-16 11:18:27 -07:00 |
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David Harris
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0a7a159d69
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Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile
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2023-05-14 06:58:29 -07:00 |
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