Ross Thompson
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a011b7d591
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Merge branch 'testbench-params2'
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2023-06-15 15:31:13 -05:00 |
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Ross Thompson
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a55bcad5c1
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 14:57:23 -05:00 |
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Ross Thompson
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3c4677ef63
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Major cleanup of testbench.
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2023-06-15 14:57:05 -05:00 |
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Ross Thompson
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e3cf1419ed
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Deleted remaining old configs except fpga as I still need to create the parameterized version.
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2023-06-15 14:08:13 -05:00 |
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Ross Thompson
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44c72c20e2
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Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
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2023-06-15 14:05:44 -05:00 |
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Ross Thompson
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2fc8080102
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Got the srams parameterized correctly now.
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2023-06-15 13:42:24 -05:00 |
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David Harris
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cdee4e9b91
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Merge pull request #337 from harshinisrinath1001/main
Fixed the spacing of the uncore and wally modules
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2023-06-15 11:33:29 -07:00 |
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Ross Thompson
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e431f90cf3
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Found a whole bunch of files still using the old `define configurations.
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2023-06-15 13:09:07 -05:00 |
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Harshini Srinath
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37c930bb27
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Update wallypipelinedsoc.sv
Program clean up
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2023-06-15 10:39:37 -07:00 |
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Harshini Srinath
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fd00067b7f
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Update wallypipelinedcore.sv
Program clean up
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2023-06-15 10:38:38 -07:00 |
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Harshini Srinath
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e3f8280ff9
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Update cvw.sv
Program clean up
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2023-06-15 10:29:33 -07:00 |
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Harshini Srinath
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e9cfbd95f4
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Update uncore.sv
Program clean up
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2023-06-15 10:23:47 -07:00 |
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Harshini Srinath
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5d8e120031
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Update uart_apb.sv
Program clean up
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2023-06-15 10:21:46 -07:00 |
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Harshini Srinath
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53ad51ae54
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Update uartPC16550D.sv
Program clean up
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2023-06-15 10:20:29 -07:00 |
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Harshini Srinath
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ae165b35f9
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Update rom_ahb.sv
Program clean up
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2023-06-15 10:13:15 -07:00 |
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Harshini Srinath
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97917c2a44
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Update ram_ahb.sv
Program clean up
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2023-06-15 10:10:38 -07:00 |
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Harshini Srinath
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a9495e8595
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Update plic_apb.sv
Program clean up
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2023-06-15 10:08:16 -07:00 |
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Harshini Srinath
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afa0bcdd16
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Update gpio_apb.sv
Program clean up
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2023-06-15 10:04:28 -07:00 |
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Harshini Srinath
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83acb77507
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Update clint_apb.sv
Program clean up
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2023-06-15 09:59:11 -07:00 |
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David Harris
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010ff382c2
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Merge pull request #332 from harshinisrinath1001/main
Fixed spacing for generic, ieu, ifu, lsu, mdu, mmu, and privileged modules and deleted CodeAligner.py
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2023-06-15 07:00:47 -07:00 |
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Ross Thompson
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d79c084a70
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Significant refactoring of testbench.
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2023-06-14 17:02:49 -05:00 |
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Ross Thompson
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7ac5239d6a
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Removed old configs from function name module.
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2023-06-14 16:35:55 -05:00 |
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Ross Thompson
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6bb5f32eb9
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Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s.
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2023-06-14 15:28:58 -05:00 |
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Ross Thompson
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19b7819d53
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Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x.
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2023-06-14 14:11:25 -05:00 |
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Harshini Srinath
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e0a30ecc22
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Merge branch 'main' into main
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2023-06-14 11:52:45 -07:00 |
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Ross Thompson
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7fb58f5cac
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more testbench improvements.
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2023-06-14 12:23:26 -05:00 |
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Ross Thompson
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8caa4dfcfb
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Continued improvements to testbench.
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2023-06-14 12:11:55 -05:00 |
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Ross Thompson
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005307fc16
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Resolved the duplicated check signature issue.
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2023-06-14 11:50:12 -05:00 |
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Ross Thompson
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c91530aa17
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Updates to wave file.
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2023-06-14 10:49:09 -05:00 |
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Harshini Srinath
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629ccb191f
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Update csrs.sv
Program clean up
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2023-06-13 22:16:43 -07:00 |
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Harshini Srinath
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49c84f888f
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Update csrm.sv
Program clean up
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2023-06-13 22:08:06 -07:00 |
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Harshini Srinath
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23eeda6370
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Update csrc.sv
Program clean up
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2023-06-13 21:59:02 -07:00 |
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Harshini Srinath
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aff15a0a46
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Update csrc.sv
Program clean up
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2023-06-13 21:54:47 -07:00 |
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Harshini Srinath
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fb019a736c
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Update csr.sv
Program clean up
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2023-06-13 21:12:49 -07:00 |
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harshini
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17724f7832
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deleting CodeAligner file
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2023-06-13 17:41:37 -07:00 |
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Ross Thompson
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5d0e86f650
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Fixed another issue with the timing of memory resets in the new testbench.
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2023-06-13 16:24:38 -05:00 |
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Ross Thompson
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ed7d785175
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Now have most of the regression tests running again.
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2023-06-13 15:09:40 -05:00 |
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Ross Thompson
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5b0467b287
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Cleaned up testbench more.
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2023-06-13 14:05:17 -05:00 |
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Ross Thompson
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7d53af9206
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Compacted memory resets.
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2023-06-13 13:57:58 -05:00 |
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Ross Thompson
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269d7b2430
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More cleanup.
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2023-06-13 13:54:07 -05:00 |
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Ross Thompson
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40f7031fe7
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Fixed the multliple reads of the same preload memory file.
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2023-06-13 13:52:02 -05:00 |
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Ross Thompson
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261b34af5d
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The testbench now at least runs the arch64i in rv64gc config. Still has several issues
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
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2023-06-13 13:18:46 -05:00 |
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David Harris
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7eaa600f45
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Merge pull request #330 from openhwgroup/revert-328-main
Revert "Update for new layout of ImperasDV files"
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2023-06-13 04:18:57 -07:00 |
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David Harris
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b83d483c9d
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Revert "Update for new layout of ImperasDV files"
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2023-06-13 04:17:56 -07:00 |
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David Harris
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2792fcf71f
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Merge pull request #328 from eroom1966/main
Update for new layout of ImperasDV files
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2023-06-13 04:04:58 -07:00 |
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Harshini Srinath
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58c617c548
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Update ahbapbbridge.sv
Program clean up
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2023-06-12 20:49:46 -07:00 |
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Harshini Srinath
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475e11e03f
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Update trap.sv
Program clean up
|
2023-06-12 20:31:44 -07:00 |
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Harshini Srinath
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e2af1fabd2
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Update privmode.sv
Program clean up
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2023-06-12 20:27:48 -07:00 |
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Harshini Srinath
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ac7043770d
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Update privileged.sv
Program clean up
|
2023-06-12 20:26:07 -07:00 |
|
Harshini Srinath
|
5f7fe5619b
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Update csru.sv
Program clean up
|
2023-06-12 20:21:55 -07:00 |
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