Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Ross Thompson
c9bdaceddb
Fixed icache for 32 bit.
...
Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Thomas Fleming
f9e071baf8
Temporarily disable rv64 mmu test
...
Will restore once cache revamp is pushed
2021-04-22 13:19:18 -04:00
Noah Boorstin
0afd5ae5f6
buildroot: add workaround for weird initial MSTATUS state
2021-04-21 16:03:42 -04:00
Domenico Ottolia
82320033d5
Add tests for stval and mtval
2021-04-21 02:31:32 -04:00
Domenico Ottolia
fed42ffe19
Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file
2021-04-21 01:12:55 -04:00
Domenico Ottolia
d5f86fadac
Add tests for sepc register
2021-04-20 23:50:53 -04:00
Ross Thompson
649589ee2c
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Noah Boorstin
c7a09d2359
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Jarred Allen
59b340dac9
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Noah Boorstin
10c7ac7f73
slowly more buildroot progress
2021-04-18 18:18:07 -04:00
Noah Boorstin
d0a137ce0c
neat verilog thing
2021-04-18 17:48:51 -04:00
Noah Boorstin
5902637632
buildroot: sim is now running!
...
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9
start to add buildroot testbench
...
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
bbracker
11cf251378
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 21:09:27 -04:00
bbracker
195cead01c
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00
Add tests for scause and ucause
2021-04-15 19:41:25 -04:00
Domenico Ottolia
8c4cfa5f69
Add 32 bit privileged tests
2021-04-15 16:55:39 -04:00
Jarred Allen
7b4b1a31ef
Merge branch 'main' into cache
2021-04-15 13:47:19 -04:00
Thomas Fleming
d281ecd067
Remove imem from testbenches
2021-04-14 20:20:34 -04:00
Jarred Allen
757b64e487
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99
rv64 interrupt servicing
2021-04-14 10:19:42 -04:00
Noah Boorstin
3e0ed5a2b1
busybear: use (slightly) less terrible verilog
2021-04-14 00:18:44 -04:00
Noah Boorstin
18a4d5fc8d
busybear testbench updates
...
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic
I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
2021-04-14 00:00:27 -04:00
Jarred Allen
357aed75ee
A few more cache fixes
2021-04-13 01:07:40 -04:00
Jarred Allen
6ce4d44ae1
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
bbracker
0c85b1c201
integrated peripheral testing into existing workflow
2021-04-08 15:31:39 -04:00
bbracker
c8c87bd0d8
merge testbench
2021-04-08 14:28:01 -04:00
Noah Boorstin
5f1cd43033
try to remove git-lfs stuff
2021-04-08 13:23:11 -04:00
Domenico Ottolia
1bdfac6a77
Cause an Illegal Instruction Exception when attempting to write readonly CSRs
2021-04-08 05:12:54 -04:00
Thomas Fleming
e807f5d771
Implement support for superpages
2021-04-08 02:44:59 -04:00
Ross Thompson
7f12c7af90
Switch to use RV64IC for the benchmarks.
...
Still not working correctly with the icache.
instr
addr correct got
2021-04-07 19:12:43 -05:00
Domenico Ottolia
9b82fbff5a
Add privileged tests to testbench
2021-04-07 02:22:08 -04:00
Domenico Ottolia
bbdd4e1467
Add passing mtval and mepc tests
2021-04-07 02:21:05 -04:00
Ross Thompson
d901cfc848
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
0a20e33971
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
Noah Boorstin
c820910b29
add busybear boot files with git-lfs
2021-04-05 19:38:43 -04:00
Noah Boorstin
ce22a1de04
busybear: reenable 'ruthless' CSR checking
2021-04-05 12:53:30 -04:00
bbracker
ce7b2314ef
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Thomas Fleming
8f31e00f6a
Merge branch 'mmu' into main
...
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-03 22:09:50 -04:00
Noah Boorstin
2f503ee6b9
busybear: temporary stop after 800k instrs
2021-04-03 21:37:57 -04:00
Katherine Parry
08b31f7b2a
Integrated FPU
2021-04-03 20:52:26 +00:00
James E. Stine
82cd900b65
Put back imperas testbench until figure out why m_supported is running for rv64ic
2021-04-02 08:19:25 -05:00
James E. Stine
9026357350
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
Thomas Fleming
06032936bd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-01 16:24:06 -04:00
Thomas Fleming
3f3d8f414d
Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu
2021-04-01 16:23:19 -04:00
Thomas Fleming
f9bf2fbc01
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
Noah Boorstin
4e62c7d5f5
busybear: temporarially stop checking CSRs
2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5
busybear: clean up questa warnings
2021-03-31 14:04:57 -04:00
