30 Commits

Author	SHA1	Message	Date
Ross Thompson	893e03d55b	Fixed memory size in configs for rv32ic and rv64ic. ... Removed warning on call to $fscanf.	2021-04-29 17:36:46 -05:00
Ross Thompson	14a69c1d06	Added the ability to exclude branch predictor.	2021-04-26 14:27:42 -05:00
bbracker	c796547156	greatly improved PLIC register interface	2021-04-22 11:22:01 -04:00
Noah Boorstin	5902637632	buildroot: sim is now running! ... yes it only gets through 5 instructions right now. Yes that's my fault.	2021-04-17 14:44:32 -04:00
bbracker	11cf251378	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-15 21:09:27 -04:00
bbracker	195cead01c	working GPIO interrupt demo	2021-04-15 21:09:15 -04:00
Domenico Ottolia	a149f2f3d8	Add support for vectored interrupts	2021-04-15 19:13:42 -04:00
Shreya Sanghai	75caa65df1	Cherry Pick merge of Shreya's localhistory predictor changes into main. ... fixed minor bugs in localHistory	2021-04-15 09:04:36 -05:00
bbracker	ce7b2314ef	Yee hoo first draft of PLIC plus self-checking tests	2021-04-04 06:40:53 -04:00
Thomas Fleming	4b2765f8e2	Complete basic page table walker	2021-03-30 22:19:27 -04:00
bbracker	eea7e2e47e	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Shreya Sanghai	dfc86539cc	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Ross Thompson	9386e6a524	Switched to gshare from global history. ... Fixed a few minor bugs.	2021-03-18 16:05:59 -05:00
Noah Boorstin	847bf0b9a6	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Noah Boorstin	fa1407f6e3	everyone gets a bootram	2021-03-18 12:35:37 -04:00
Shreya Sanghai	d9b1e7d67f	added gshare and global history predictor	2021-03-16 17:03:01 -04:00
Shreya Sanghai	a79e26f9d8	added global history branch predictor	2021-03-16 16:06:40 -04:00
Shreya Sanghai	518618ad38	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Ross Thompson	8e51935082	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
David Harris	bea8ac6d59	WALLY-LRSC atomic test passing	2021-03-09 09:28:25 -05:00
Shreya Sanghai	7cd8f1a592	added performance counters	2021-03-04 11:42:52 -05:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	9511dcac84	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	9530039e3d	Implemented adrdec for uncore	2021-01-29 17:28:53 -05:00
David Harris	e4e95bf941	Added ahblite bus interface unit	2021-01-29 01:07:17 -05:00
David Harris	4318629b32	Repartitioned datapath and controller into ieu	2021-01-27 06:40:26 -05:00
David Harris	b7988e536f	Reset Vector moved to config file	2021-01-25 15:57:36 -05:00
David Harris	bf07ec92b5	Added test configurations	2021-01-25 11:28:43 -05:00