Teo Ene
b15ef47d24
Fix to 32-bit option of commit 2d40898158
2021-03-04 01:33:34 -06:00
Teo Ene
0c009fb1e6
In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches
2021-03-04 01:27:05 -06:00
Thomas Fleming
d821a1dbfa
Merge branch 'main' into tlb_toy
2021-03-04 01:18:04 -05:00
Thomas Fleming
c03b540956
Generalize tlb module
...
- number of tlb entries is now parameterized
- tlb now supports rv64i
2021-03-04 01:13:31 -05:00
Teo Ene
a82a123069
Implemented fix disucssed with Elizabeth
2021-03-03 18:17:53 -06:00
Thomas Fleming
692d4152fa
Begin hardware page table walker
2021-03-03 17:13:45 -05:00
Thomas Fleming
5fd521d333
Create virtual memory ad-hoc test
...
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
2021-03-03 17:06:37 -05:00
Teo Ene
d3a1afe50e
Fix to last push
2021-03-03 15:20:38 -06:00
Teo Ene
b50faef94d
Updated coremark .do file for easier debugging
2021-03-03 15:10:39 -06:00
Teo Ene
e30645a4f1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-02 17:23:44 -06:00
Teo Ene
d02e22feac
Updated coremark .do file for easier debugging
2021-03-02 17:23:39 -06:00
Noah Boorstin
beb2beabfd
busybear: add sim-busybear and sim-busybear-batch based on sim-wally
2021-03-01 21:01:15 +00:00
Noah Boorstin
923489fe16
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
b6dc0a8707
busybear: only check pc when it actually changes
2021-03-01 19:08:35 +00:00
Noah Boorstin
b3247eadd2
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
Noah Boorstin
f11b3108d8
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
David Harris
23a1cf63b3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-01 00:09:55 -05:00
David Harris
6f4e8b723e
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Teo Ene
2d40898158
Properly implemented the fix from commit 5fee65231e
2021-02-28 22:22:04 -06:00
Noah Boorstin
141f6a5496
Merge branch 'main' into busybear
2021-02-28 20:48:23 +00:00
Noah Boorstin
a5f1dbfe23
add .nfs* files to gitignore
2021-02-28 20:48:01 +00:00
Noah Boorstin
a267115635
Merge branch 'main' into busybear
2021-02-28 20:45:08 +00:00
Noah Boorstin
17715085ba
busybear: start preloading bootmem
2021-02-28 20:43:57 +00:00
Noah Boorstin
932bc0ef85
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
856a1079cc
busybear: change sstatus, mstatus reset value
2021-02-28 16:19:03 +00:00
Noah Boorstin
2769b147cb
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489
busybear: remove gpio, start adding 2nd ram
2021-02-28 06:02:40 +00:00
Noah Boorstin
0596d61a2a
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
0258901865
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
kaveh pezeshki
e8b306bcba
merged with main to integrate with AHB
2021-02-26 05:37:10 -08:00
Noah Boorstin
4c7b185d90
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
kaveh Pezeshki
2782ca2480
fixed sensitivity list on error checking always block, removed useless once and for all
2021-02-26 13:41:16 -05:00
kaveh pezeshki
adadc21fc6
restored
2021-02-26 02:22:08 -08:00
David Harris
225102047a
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
1b61d78ac2
Retimed peripherals for AHB interface
2021-02-26 00:55:41 -05:00
Brett Mathis
87e4311339
Fcmp/Fsgn pipeline modules
2021-02-25 18:22:30 -06:00
David Harris
bad180fc15
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-25 15:49:38 -05:00
David Harris
f57096a5d2
Restored to working multiplier after Lab 2
2021-02-25 15:32:43 -05:00
Brett Mathis
b0a5052bcf
FPU Assembly tests
2021-02-25 14:32:36 -06:00
Teo Ene
a35fdac75b
Fixed previous commit
2021-02-25 11:24:44 -06:00
Teo Ene
5fee65231e
Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.
2021-02-25 11:23:01 -06:00
Teo Ene
b9701293a0
Changed TIMBASE in coremark config file
2021-02-25 11:03:41 -06:00
Teo Ene
a6c16af721
Merge remote-tracking branch 'origin/lab3' into main
2021-02-25 10:28:20 -06:00
Teo Ene
8491deb1a9
Changed .do file back to run all
2021-02-25 09:58:54 -06:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
eb52fd1c5a
removed WALLY ALU tests to avoid merge conflict with main branch
2021-02-25 00:15:22 -05:00
Teo Ene
cfd45a46c3
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
