Ross Thompson
97c73f10ff
Fixed uart for FPGA config after merge. This still needs some work.
2021-11-29 16:07:54 -06:00
Ross Thompson
a871118116
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
Noah Limpert
09d3322a26
updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well
2021-11-24 23:22:04 -08:00
Noah Limpert
93b626ce2a
replaced .* instation of priv module on wallypiplinedhart
2021-11-24 22:58:59 -08:00
Noah Limpert
f36cc7a2a3
Made abhlite instation on wallypipehart more clear, updated spacing for consistency
2021-11-24 22:48:01 -08:00
Noah Limpert
5b7c969170
updated module instation of LSU on wallypiplinedhard
2021-11-24 22:09:39 -08:00
Ross Thompson
1183aed049
Missed another change to uart.
2021-11-23 10:20:47 -06:00
Ross Thompson
3fc370654d
Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
2021-11-23 10:00:32 -06:00
Ross Thompson
f12e7e1b68
Added QEMU hack for initial LCR value in uart.
2021-11-22 15:23:19 -06:00
Ross Thompson
f05a66acd1
Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed.
2021-11-22 15:20:54 -06:00
Ross Thompson
d5cf6da6eb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-22 11:30:14 -06:00
bbracker
cffb72042a
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
Ross Thompson
e955b17500
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:44:45 -06:00
Ross Thompson
9d3261ed49
Reversed bit order in uart.
2021-11-20 22:43:05 -06:00
Ross Thompson
705572f0ac
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
...
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
slmnemo
0bf1836a3a
Removed .* from hazard hzu(.*).
2021-11-17 14:21:23 -08:00
slmnemo
5c28553ca1
Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
2021-11-17 14:08:08 -08:00
slmnemo
df6c54a664
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:38:51 -08:00
slmnemo
bf8cef78bc
removed .* from muldiv.sv (REAL)
2021-11-17 13:37:50 -08:00
Noah Limpert
b63c0f35d1
ieu variable naming changed for clarity
2021-11-17 13:24:28 -08:00
slmnemo
c5c886ddc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:23:20 -08:00
slmnemo
40efffc70b
Removed .*s from muldiv.sv
2021-11-17 13:23:12 -08:00
Noah Limpert
70a84b56c8
Updated IFU variable naming for clarity
2021-11-17 12:39:05 -08:00
Kip Macsai-Goren
7a8c21e71f
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Ross Thompson
f4c221f20a
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
Ross Thompson
23e78c4842
Fixed uart by reversing the bit order on transmit.
...
Set prescale to 0.
2021-11-17 10:32:41 -06:00
Ross Thompson
1c9670d739
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
2021-11-12 17:37:07 -06:00
Ross Thompson
7497422667
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Kevin
11efaa2669
changed code aligner to run recursively on a root directory
...
-only runs the aligner on .sv files
-runs recursively on sub-directories
2021-11-03 10:49:34 -07:00
David Harris
dda035891a
PIPELINE test running
2021-11-01 12:44:35 -07:00
Ross Thompson
9c875d38a9
Fixed the 4 way set associative pseudo LRU replacement policy.
2021-10-29 12:46:02 -05:00
Ross Thompson
41dbb59e24
Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
2021-10-29 11:03:37 -05:00
Ross Thompson
35fcadbe7f
Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
2021-10-28 11:07:18 -05:00
Noah Limpert
27251a9935
Have replaced .* with signal names in ifu
2021-10-27 13:45:37 -07:00
koooo142857
33f5de0f5c
aligned all files in ifu folder
2021-10-27 12:43:55 -07:00
David Harris
582c2bf37b
Fixed FResultSelM to select proper flags
2021-10-27 11:02:42 -07:00
Ross Thompson
c4170ece27
Replaced async reset flip flops with sync reset flip flops in cache and bpread.
2021-10-27 09:57:11 -05:00
Ross Thompson
400670cb06
Linux now boots fpga.
2021-10-26 16:49:16 -05:00
David Harris
426a43f77b
Forgot to save cacheway merge
2021-10-26 08:38:13 -07:00
David Harris
c0145c0a35
merging changes
2021-10-26 08:34:36 -07:00
David Harris
8287a1ef3e
Synchronous reset in non-flop blocks
2021-10-26 08:30:35 -07:00
Ross Thompson
c43b19120f
Fixed another critical path in the caches.
2021-10-25 22:05:11 -05:00
Ross Thompson
1228dbbebc
Fixed the timing issue in the cache replacement polcy.
2021-10-25 18:00:23 -05:00
Ross Thompson
576383c74b
Fixed bug with the changes to sram1rw.
2021-10-25 16:11:41 -05:00
Ross Thompson
f0beb4357a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-25 15:36:21 -05:00
Ross Thompson
5fd3f7f2c7
Possible fix for critical path timing in caches.
2021-10-25 15:33:33 -05:00
Ross Thompson
81054d9168
Fixed issue with dtim (fpga) external abhlite select not triggering.
...
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
bbracker
39efadf2cf
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-25 12:25:37 -07:00
Ross Thompson
32f0b97cd3
Updated uncore to use sdc.
...
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
