mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
PIPELINE test running
This commit is contained in:
David Harris
parent
60573b92b2
commit
dda035891a
@ -1,6 +1,6 @@
|
||||
#!/usr/bin/python3
|
||||
##################################
|
||||
# wally-I-PIPELINE.py
|
||||
# PIPELINE.py
|
||||
#
|
||||
# David_Harris@hmc.edu 27 October 2021
|
||||
#
|
||||
@ -108,7 +108,7 @@ for xlen in xlens:
|
||||
storecmd = "sd"
|
||||
wordsize = 8
|
||||
pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
|
||||
fname = pathname + "src/WALLY-PIPELINE.S"
|
||||
fname = pathname + "src/PIPELINE.S"
|
||||
testnum = 0
|
||||
|
||||
# print custom header part
|
||||
@ -126,6 +126,19 @@ for xlen in xlens:
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
maxreg = 5
|
||||
for i in range(1):
|
||||
instr = instrs[randint(0,len(instrs)-1)]
|
||||
reg1 = randint(0,maxreg)
|
||||
reg2 = randint(0,maxreg)
|
||||
reg3 = randint(1,maxreg)
|
||||
line = instr + " x" +str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
|
||||
f.write(line)
|
||||
|
||||
for i in range(1,maxreg+1):
|
||||
line = storecmd + " x" + str(i) + ", " + str(wordsize*(i-1)) + "(x8)\n"
|
||||
f.write(line)
|
||||
|
||||
# print directed and random test vectors
|
||||
# for a in corners:
|
||||
# for b in corners:
|
||||
@ -1,3 +1,4 @@
|
||||
#endif
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
|
||||
@ -87,7 +87,7 @@ simulate:
|
||||
run -C $(SUITEDIR)
|
||||
|
||||
verify: simulate
|
||||
riscv-test-env/verify.sh
|
||||
# riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values
|
||||
|
||||
postverify:
|
||||
ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),)
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
///////////////////////////////////////////
|
||||
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S
|
||||
// David_Harris@hmc.edu
|
||||
// Created 2021-11-01 08:46:04.665699//
|
||||
// Created 2021-11-01 11:43:39.219968//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
@ -32,6 +32,13 @@ RVTEST_CODE_BEGIN
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
|
||||
|
||||
RVTEST_SIGBASE( x8,signature_x8_1)
|
||||
AND x1, x3, x3
|
||||
sw x1, 0(x8)
|
||||
sw x2, 4(x8)
|
||||
sw x3, 8(x8)
|
||||
sw x4, 12(x8)
|
||||
sw x5, 16(x8)
|
||||
#endif
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
|
||||
@ -29,6 +29,7 @@
|
||||
|
||||
rv64i_sc_tests = \
|
||||
add-01 \
|
||||
PIPELINE \
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,82 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S
|
||||
// David_Harris@hmc.edu
|
||||
// Created 2021-11-01 08:46:04.668632//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV64I")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
|
||||
|
||||
RVTEST_SIGBASE( x8,signature_x8_1)
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
|
||||
|
||||
signature_x8_0:
|
||||
.fill 0*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x8_1:
|
||||
.fill 19*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 256*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 256*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_2:
|
||||
.fill 148*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
RVMODEL_DATA_END
|
||||
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S
|
||||
// David_Harris@hmc.edu
|
||||
@ -55,7 +55,7 @@ module fpudivsqrtrecur (
|
||||
// Special Cases
|
||||
// *** shift to handle denorms in hardware
|
||||
|
||||
assign FDivSqrtResSign = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs
|
||||
assign FDivSqrtResSgn = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs
|
||||
|
||||
always_comb begin
|
||||
if (FSqrtE & XSgnE | FDivE & XZeroE & YZeroE | XNaNE | FDivE & YNaNE) FDivSqrtResM = 0; // ***replace with NAN; // *** which one
|
||||
|
||||
@ -64,7 +64,10 @@ module intdiv #(parameter WIDTH=64)
|
||||
logic [WIDTH-1:0] QT, remT;
|
||||
logic D_NegOne;
|
||||
logic Max_N;
|
||||
|
||||
|
||||
logic otfzerov;
|
||||
logic tcQ;
|
||||
logic tcR;
|
||||
|
||||
// Check if negative (two's complement)
|
||||
// If so, convert to positive
|
||||
@ -182,7 +185,9 @@ module divide4 #(parameter WIDTH=64)
|
||||
logic CshiftQ, CshiftQM;
|
||||
logic [WIDTH+3:0] rem1, rem2, rem3;
|
||||
logic [WIDTH+3:0] SumR, CarryR;
|
||||
logic [WIDTH:0] Qt;
|
||||
logic [WIDTH:0] Qt;
|
||||
|
||||
logic ulp;
|
||||
|
||||
// Create one's complement values of Divisor (for q*D)
|
||||
assign divi1 = {3'h0, op2, 1'b0};
|
||||
|
||||
@ -1071,8 +1071,8 @@ string imperas32f[] = '{
|
||||
|
||||
string wally64i[] = '{
|
||||
`WALLYTEST,
|
||||
"rv64i_m/I/add-01", "9010"
|
||||
// "rv64i_m/I/pipeline-01", "9010"
|
||||
"rv64i_m/I/add-01", "9010",
|
||||
"rv64i_m/I/PIPELINE", "2010"
|
||||
};
|
||||
|
||||
string wally64priv[] = '{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user