Ross Thompson 23e78c4842 Fixed uart by reversing the bit order on transmit. ... Set prescale to 0.		2021-11-17 10:32:41 -06:00
..
cache	Updated uncore to use sdc.	2021-10-25 14:07:44 -05:00
ebu	Additional cleanup of ahblite.	2021-08-25 22:53:20 -05:00
fpu	Merge branch 'main' into fpga	2021-10-22 16:09:16 -05:00
generic	Changed several things.	2021-11-12 11:13:50 -06:00
hazard	The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.	2021-09-17 10:33:57 -05:00
ieu	Added more pipeline stage suffixes to divider	2021-10-02 22:54:01 -04:00
ifu	simplify flopenrc's that didn't actually need to be flopenrc's	2021-10-10 12:25:05 -07:00
lsu	Finished adding the d cache flush. Required ensuring the write data, address, and size are	2021-09-17 13:03:04 -05:00
mmu	Merge branch 'main' into fpga	2021-10-20 16:24:55 -05:00
muldiv	Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this	2021-10-19 12:09:43 -05:00
privileged	Merge branch 'main' into fpga	2021-10-20 16:24:55 -05:00
sdc	Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.	2021-11-12 17:37:07 -06:00
uncore	Fixed uart by reversing the bit order on transmit.	2021-11-17 10:32:41 -06:00
wally	Changed several things.	2021-11-12 11:13:50 -06:00