Ross Thompson 97c73f10ff Fixed uart for FPGA config after merge. This still needs some work.		2021-11-29 16:07:54 -06:00
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cache	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
ebu	Lint cleanup: ahblite, ifu, hart	2021-10-23 10:12:33 -07:00
fpu	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
generic	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
hazard	IEU cleanup	2021-10-23 11:13:28 -07:00
ieu	renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv	2021-11-17 10:53:17 -08:00
ifu	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
lsu	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
mmu	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
muldiv	Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.	2021-11-17 14:08:08 -08:00
privileged	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
sdc	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
uncore	Fixed uart for FPGA config after merge. This still needs some work.	2021-11-29 16:07:54 -06:00
wally	Merge branch 'main' into fpga	2021-11-29 10:10:37 -06:00