167 Commits

Author	SHA1	Message	Date
Teo Ene	95ce4b7daa	Edited assemby of bare-metal coremark to make it run	2021-03-04 07:45:40 -06:00
Teo Ene	2723b21988	Linux CoreMark and baremetal CoreMark split into two separate tests/configs	2021-03-04 07:44:33 -06:00
Teo Ene	80f6d6c944	Linux CoreMark is operational	2021-03-04 05:58:18 -06:00
Teo Ene	0c009fb1e6	In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches	2021-03-04 01:27:05 -06:00
Teo Ene	a82a123069	Implemented fix disucssed with Elizabeth	2021-03-03 18:17:53 -06:00
Teo Ene	d3a1afe50e	Fix to last push	2021-03-03 15:20:38 -06:00
Teo Ene	b50faef94d	Updated coremark .do file for easier debugging	2021-03-03 15:10:39 -06:00
Teo Ene	e30645a4f1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-02 17:23:44 -06:00
Teo Ene	d02e22feac	Updated coremark .do file for easier debugging	2021-03-02 17:23:39 -06:00
David Harris	23a1cf63b3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-01 00:09:55 -05:00
David Harris	6f4e8b723e	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
Teo Ene	2d40898158	Properly implemented the fix from commit 5fee65231e	2021-02-28 22:22:04 -06:00
David Harris	73920282af	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	0258901865	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	225102047a	Clean up bus interface code	2021-02-26 01:03:47 -05:00
David Harris	1b61d78ac2	Retimed peripherals for AHB interface	2021-02-26 00:55:41 -05:00
David Harris	bad180fc15	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-25 15:49:38 -05:00
David Harris	f57096a5d2	Restored to working multiplier after Lab 2	2021-02-25 15:32:43 -05:00
Brett Mathis	b0a5052bcf	FPU Assembly tests	2021-02-25 14:32:36 -06:00
Teo Ene	a35fdac75b	Fixed previous commit	2021-02-25 11:24:44 -06:00
Teo Ene	5fee65231e	Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.	2021-02-25 11:23:01 -06:00
Teo Ene	b9701293a0	Changed TIMBASE in coremark config file	2021-02-25 11:03:41 -06:00
Teo Ene	8491deb1a9	Changed .do file back to run all	2021-02-25 09:58:54 -06:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
Teo Ene	cfd45a46c3	Added provisional coremark files from work with Elizabeth	2021-02-24 20:07:07 -06:00
David Harris	38b8cc652c	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
Katherine Parry	07641203ee	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-23 20:21:53 +00:00
Katherine Parry	906ec30339	inital FMA push	2021-02-23 20:19:12 +00:00
David Harris	7737b0f709	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
David Harris	f372e2b8e8	Debugging Bus interface	2021-02-22 13:48:30 -05:00
David Harris	87ad559a90	Updated creation date of mul	2021-02-18 08:13:08 -05:00
David Harris	fe7299c155	Resotred part of multiplier for lab 2	2021-02-17 16:14:04 -05:00
David Harris	492ec0ee78	Removed multiplier for lab 2	2021-02-17 16:06:16 -05:00
David Harris	e8d3c7d9e7	Multiplier tweaks	2021-02-17 16:00:27 -05:00
David Harris	e64e8afb7f	Started to integrate OSU divider	2021-02-17 15:38:44 -05:00
David Harris	a7dd20b388	Multiply instructions working	2021-02-17 15:29:20 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	3900abeb86	WALLY ALU tests	2021-02-15 10:16:31 -05:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
Domenico Ottolia	3ee975dd5a	Add privileged test cases	2021-02-14 17:01:46 -05:00
Shreya Sanghai	4e887f83a3	added branch tests	2021-02-12 22:40:08 -05:00
bbracker	deb7780897	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
Tejus Rao	fb6a4bbbf0	added test cases for ADDW, SUBW, SLLW, SRLW, SRAW	2021-02-11 13:38:38 -05:00
Teo Ene	5f84ed407c	Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts	2021-02-10 20:48:39 -06:00
ethan-falicov	7925fe3131	Fixed merge conflict stuff	2021-02-10 10:03:30 -05:00
ethan-falicov	06517631cc	More merge conflicts yay	2021-02-10 09:54:30 -05:00
ethan-falicov	863796b3c1	Merge conflict fixing	2021-02-10 09:45:47 -05:00
ethan-falicov	67662b888e	Adding I Type test cases from Lab 1	2021-02-10 09:39:43 -05:00
David Harris	b121b90b28	Debugging bus interface.	2021-02-10 01:43:54 -05:00
David Harris	842c374de9	Debugging instruction fetch	2021-02-09 11:02:17 -05:00