David Harris
c4400dfeb0
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
2024-07-22 08:45:08 -07:00
Jordan Carlin
032de34dbd
Lint fixes for no priv mode configs
2024-06-26 22:15:18 -07:00
David Harris
3fa37b0233
Lint cleanup
2024-06-18 06:15:17 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
...
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
3f195884e9
Defined bit sizes more precisely to help VCS lint and conform to coding style
2024-04-21 08:40:11 -07:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
James E. Stine
141cbd3f9f
Update marchid/mvendorid for CV-Wally
2023-11-21 09:23:02 -06:00
David Harris
f6a7f707bd
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
2023-10-30 09:56:17 -07:00
David Harris
27b8ebb9bd
Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.
2023-10-30 07:06:34 -07:00
David Harris
434d6b2c5c
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
Ross Thompson
af0e33209f
Removed QEMU from configurations.
2023-07-19 10:23:55 -05:00
David Harris
e713ba8d3e
MENVCFG only exists if U_SUPPORTED
2023-07-09 18:25:07 -07:00
David Harris
869a7cb827
Removed MTINST, which is not used in a system without a hypervisor
2023-07-06 12:40:53 -07:00
David Harris
b6ae5661b4
Added environment configuration control (menvcfg/senvcfg) of cbo instructions
2023-07-02 01:52:25 -07:00
David Harris
15314a9c9a
Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
2023-07-02 00:34:30 -07:00
Harshini Srinath
3593762cfa
Merge branch 'main' into main
2023-06-14 11:52:45 -07:00
Harshini Srinath
12af05da02
Update csrm.sv
...
Program clean up
2023-06-13 22:08:06 -07:00
Harshini Srinath
6305412d57
Update csrm.sv
...
Program clean up
2023-06-12 19:42:45 -07:00
David Harris
b70b0c7c5e
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
2023-06-09 14:40:01 -07:00
Ross Thompson
c7e515634d
I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.
2023-05-26 13:56:51 -05:00
Ross Thompson
8cf38b28aa
The privileged unit is parameterized using Lim's method.
2023-05-26 12:03:46 -05:00
David Harris
52f49ed24d
Fault on writes to odd-numbered PMPCFG in RV64
2023-04-22 15:32:39 -07:00
David Harris
da53f240d3
Refactored InstrValidNotFlushed into CSR Write signals
2023-03-30 17:06:09 -07:00
Kip Macsai-Goren
3805cf993a
unnecessary comments cleanup
2023-03-29 19:32:57 -07:00
Kip Macsai-Goren
491ef14b71
Resolved ImperasDV receiving incorrect cause values
2023-03-29 15:04:56 -07:00
David Harris
9d8f9e4428
Reduced number of bits in mcause and medeleg registers
2023-03-29 07:02:09 -07:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
David Harris
a1eccf37dc
Fix Issue 145
2023-03-22 04:33:14 -07:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
