David Harris
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8fbdbba81a
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fma file fixes
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2022-03-02 23:47:01 +00:00 |
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bbracker
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be2f668867
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but apparently QEMU doesn't show UXL in SSTATUS
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2022-03-02 22:44:19 +00:00 |
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bbracker
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01e0f2f0d2
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update SXL UXL bits in MSTATUS to match new QEMU trace
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2022-03-02 22:15:57 +00:00 |
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David Harris
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3bea7bb431
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removed imperas-riscv-tests
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2022-03-02 17:28:20 +00:00 |
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David Harris
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1661983345
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FMA project ready to start
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2022-03-01 20:58:08 +00:00 |
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David Harris
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f314e60dc8
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Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
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2022-02-28 20:50:51 +00:00 |
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David Harris
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f0a7ae2bba
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adrdecs comments
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2022-02-28 20:33:41 +00:00 |
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David Harris
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e108eb5195
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Modified address decoder for native access to CLINT
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2022-02-28 19:13:14 +00:00 |
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David Harris
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3519a20ccf
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hptw cleanup for synthesis
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2022-02-28 05:54:34 +00:00 |
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David Harris
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bb14dba9be
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Created softfloat_demo showcasing how to do math with SoftFloat
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2022-02-27 18:17:21 +00:00 |
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David Harris
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c7b5d32a72
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Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior
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2022-02-27 17:23:33 +00:00 |
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David Harris
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c6561d1e8b
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Moved FMA back into source tree to facilitate synthesis
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2022-02-27 15:41:41 +00:00 |
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David Harris
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274ecf13ad
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Moved fma directory
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2022-02-27 14:20:15 +00:00 |
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David Harris
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5a5142c14f
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fma simulation infrastructure
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2022-02-27 04:36:43 +00:00 |
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David Harris
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d917cc1379
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fma passing multiply vectors
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2022-02-27 04:36:01 +00:00 |
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David Harris
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8a55935456
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simplified fma Makefile
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2022-02-26 19:55:42 +00:00 |
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David Harris
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1852eccaab
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Made softfloat.a a symlink
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2022-02-26 19:53:04 +00:00 |
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David Harris
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87d1a8a1ac
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Added start of fma
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2022-02-26 19:51:19 +00:00 |
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Ross Thompson
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97d64201f7
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Fixed bug with DAPageFault being wrong when HPTW writes not supported.
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2022-02-23 10:54:34 -06:00 |
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Ross Thompson
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53f13d4cbc
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More spillsupport more structual.
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2022-02-23 10:27:14 -06:00 |
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Ross Thompson
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c23f6c7d90
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Fixed bug with spill support and Instruction DA Page Faults.
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2022-02-23 10:16:12 -06:00 |
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Ross Thompson
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62e1a97287
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Added generates to pcnextf muxes for privileged and caches.
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2022-02-22 22:45:00 -06:00 |
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Ross Thompson
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6a52f95cc8
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Minor busdp cleanup.
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2022-02-22 17:28:26 -06:00 |
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Ross Thompson
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59a2c09c5e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-22 14:45:53 -06:00 |
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Ross Thompson
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90be3d4360
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Clarified interlockfsm.
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2022-02-22 11:31:28 -06:00 |
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bbracker
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b8fd06576c
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fix lint bugs in PLIC and UART
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2022-02-22 05:04:18 +00:00 |
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bbracker
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a6047697c3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-02-22 04:27:50 +00:00 |
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bbracker
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e7934c585a
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change RX side of UART to aslo be LSB-first
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2022-02-22 03:34:08 +00:00 |
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Ross Thompson
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3a29504279
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Added some clearity to lsuvirtmem.sv.
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2022-02-21 17:20:58 -06:00 |
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Ross Thompson
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ca59778c5a
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Annotated IFU for mux changes.
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2022-02-21 17:20:34 -06:00 |
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Ross Thompson
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2f711fb642
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Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
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2022-02-21 16:54:38 -06:00 |
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Ross Thompson
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0c65ea96d8
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Cleaned up names in lsuvirtmem.
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2022-02-21 16:44:30 -06:00 |
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Ross Thompson
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56fc6d0d7c
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Minor cleanup of lsu.
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2022-02-21 12:46:06 -06:00 |
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Ross Thompson
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f48b12b089
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Moved mux into lsuvirtmem.
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2022-02-21 09:31:29 -06:00 |
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Ross Thompson
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cbf4395457
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-21 09:06:09 -06:00 |
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Ross Thompson
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ae06785b9f
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Minor changes to LSU.
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2022-02-19 14:38:17 -06:00 |
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David Harris
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20a5798f43
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-02-18 23:08:47 +00:00 |
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David Harris
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6a0ffff05d
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Removed problematic warning about reaching default state in HPTW
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2022-02-18 23:08:40 +00:00 |
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Ross Thompson
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6cd9d84e7f
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New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
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2022-02-17 17:19:41 -06:00 |
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Ross Thompson
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ad237b3ce5
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Accidentally cleared dirty bit when setting access bit in hptw.
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2022-02-17 16:20:20 -06:00 |
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Ross Thompson
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cbac34943c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-17 14:49:37 -06:00 |
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Ross Thompson
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0eec096474
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Rough implementation passing regression test with hptw atomic writes to memory.
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2022-02-17 14:46:11 -06:00 |
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David Harris
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f3c7025ade
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Started make allsynth to try many experiments
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2022-02-17 17:57:02 +00:00 |
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Ross Thompson
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2fc7dc3e57
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Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
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2022-02-17 10:04:18 -06:00 |
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Ross Thompson
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62f5f1e622
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Broken state. address translation not working after changes to hptw to support atomic updates to PT.
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2022-02-16 23:37:36 -06:00 |
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Ross Thompson
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c9e33208e3
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Moved a few muxes around after sww changes.
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2022-02-16 15:43:03 -06:00 |
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Ross Thompson
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71ed49bf2b
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cleanup of signal names.
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2022-02-16 15:29:08 -06:00 |
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Ross Thompson
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6dc12b4968
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-16 15:22:35 -06:00 |
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Ross Thompson
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27042f028e
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Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
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2022-02-16 15:22:19 -06:00 |
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David Harris
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c23db6a31e
|
Cleaned warning on HPTW default state
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2022-02-16 17:40:13 +00:00 |
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