kwan
8f79a12cbb
priviledge .* removed, passed regression
2021-12-13 00:34:43 -08:00
kwan
f0e425e4ea
test
2021-12-13 00:31:51 -08:00
kwan
a365e86197
priviledge .* fixed, passed local regression
2021-12-13 00:22:01 -08:00
Kevin
03274de97c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-12 17:53:41 -08:00
Kevin
98420cb988
dot stars conversions on the rest of the testbenches
2021-12-12 17:53:26 -08:00
Ross Thompson
051dd7d09d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:33:29 -06:00
Ross Thompson
395766219b
Revert "Privilige .*s removed"
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This reverts commit 82bab8e90e
2021-12-12 17:31:57 -06:00
Ross Thompson
f758a53247
Revert "Priviledged .* removed"
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This reverts commit a95efea0b3
2021-12-12 17:31:39 -06:00
Ross Thompson
39168a201b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:21:51 -06:00
Ross Thompson
68745d40f2
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
f2628494e3
Missed constraints file for xilinx ILA.
2021-12-12 15:06:29 -06:00
Ross Thompson
545c586186
Added proper credit to Richard Davis, the author of the original sd card reader.
2021-12-12 15:05:50 -06:00
kwan
a95efea0b3
Priviledged .* removed
2021-12-12 09:55:45 -08:00
kwan
82bab8e90e
Privilige .*s removed
2021-12-12 09:54:14 -08:00
Kevin
1a82b50483
edited one testbench, yet to run regression
2021-12-10 20:26:20 -08:00
Ross Thompson
4cea8d1a29
Performance counters now output of coremark.
2021-12-09 14:48:17 -06:00
Ross Thompson
37079626cd
Fixed numerous errors in the preformance counter updates.
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Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
2021-12-09 11:44:12 -06:00
bbracker
f7b2d3b6df
fix recursive signal logging for graphical sims
2021-12-08 16:07:26 -08:00
bbracker
d6ae6824ab
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 14:12:18 -08:00
bbracker
f8cffca2b2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 14:12:09 -08:00
bbracker
5feccaec68
fix release of ReadDataM
2021-12-08 14:11:43 -08:00
slmnemo
e39f94b645
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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help
2021-12-08 14:09:58 -08:00
slmnemo
f2f15c0495
Removed .* from /wally-pipelined/src/uncore/uart.sv
2021-12-08 14:02:53 -08:00
Ross Thompson
f1ea52cb2d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 15:50:43 -06:00
Ross Thompson
741a21d0df
Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.
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Remove preload from dtim.
2021-12-08 15:50:15 -06:00
Noah Limpert
5f0521d497
updated fcmp.sv instantiation to remove x*'s
2021-12-08 13:34:33 -08:00
Ross Thompson
8b7cefab79
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 13:40:44 -06:00
Ross Thompson
9ddd065340
Updated coremark testbench with the extra ports from FPGA merge.
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Fixed coremark Makefile to create work directory.
2021-12-08 13:40:32 -06:00
bbracker
255cc26126
increase regression's expectations of buildroot to 246 million
2021-12-08 07:01:22 -08:00
slmnemo
7d614869a1
Removed .*s from wally-pipelined/src/uncore/uncore.sv
2021-12-08 01:03:02 -08:00
slmnemo
f413ea1b4a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 00:26:13 -08:00
Noah Limpert
15bdf5680e
removed .* instantiation from ieu.sv and datapth.sv in ieu folder
2021-12-08 00:24:27 -08:00
slmnemo
021faaf8cd
Removed .* from mmu instance inside lsu.sv.
2021-12-08 00:15:30 -08:00
Katherine Parry
80f026a734
FMA uses one LOA
2021-12-07 14:15:43 -08:00
bbracker
5a611bd82d
undo intentionally breaking commit
2021-12-07 13:43:47 -08:00
bbracker
5d90f899b8
intentionally breaking commit
2021-12-07 13:27:34 -08:00
bbracker
c9808988c1
undo intentionally breaking commit
2021-12-07 13:27:06 -08:00
bbracker
2b41e37160
intentionally breaking commit
2021-12-07 13:23:19 -08:00
bbracker
8f73c1df9e
2nd attempt at making regression-wally.py able to be run from a different dir
2021-12-07 13:13:30 -08:00
bbracker
979580b1e7
fix checkpointing so that it can find the synchronized reset signal
2021-12-07 13:12:06 -08:00
bbracker
302bc56646
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-07 11:16:51 -08:00
bbracker
010339fa05
attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly
2021-12-07 11:16:43 -08:00
Ross Thompson
4dbd5d45ee
Added information on how to copy the linux image to flash card.
2021-12-07 13:16:38 -06:00
bbracker
2229e66d6c
add buildroot tv linking to make-tests.sh
2021-12-07 11:15:59 -08:00
Ross Thompson
6c6b7865fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-07 13:12:59 -06:00
Ross Thompson
22721dd923
Added generate around the dtim preload.
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Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e
Fixed two issues.
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First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
bbracker
5a73ecd0be
regression.py bugfix
2021-12-06 19:32:38 -08:00
bbracker
4df9093a7f
add make-tests scripts
2021-12-06 15:37:33 -08:00
bbracker
7c44ecb364
add buildroot-only option to regression
2021-12-06 14:13:58 -08:00
