Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Added generate around the dtim preload.

Browse Source 
Added readme to explain FPGA.
This commit is contained in:
Ross Thompson 2021-12-07 13:12:47 -06:00
parent 29743c5e9e
commit 22721dd923
2 changed files with 90 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
fpga/README.md Normal file
View File

@ -0,0 +1,40 @@
The FPGA currently only targets the VCU118 board.
* Build Process
cd generator
make
* Description
The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4,
axi_clock_converter, and ahblite_axi_bridge. Then it reads in the 4 IP blocks
and builds wally. fpga/src/fpgaTop.v is the top level which instanciates
wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic
analyzer) which provides the current instruction PCM, instrM, etc along with
a large number of debuging signals.
* Loading the FPGA
After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's
gui and open the WallyFPGA.xpr project file. Open the hardware manager under
program and debug. Open target and then program with the bit file.
* Test Run
Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide
status of the reset and ddr4 calibration. LED 7 should always be lit.
LED 6 will light if the DDR4 is not calibrated. LED 6 will be lit once
wally begins running.
Next the bootloader program will copy the flash card into the DDR4 memory.
When this done the lower 5 LEDs will blink 5 times and then try to boot
the program loaded in the DDR4 memory at physical address 0x8000_0000.
* Connecting uart
You'll need to connect both usb cables. The first connects the FPGA programer
while the connect connects UART. UART is configured to use 57600 baud with
no parity, 8 data bits, and 1 stop bit. sudo screen /dev/ttyUSB1 57600 should
let you view the com port.

96
wally-pipelined/src/uncore/dtim.sv
View File

@ -49,52 +49,56 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
logic memwrite;
logic [3:0] busycount;
initial begin
//$readmemh(PRELOAD, RAM);
// FPGA only
RAM[0] = 64'h94e1819300002197;
RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301;
RAM[3] = 64'h4681460145814501;
RAM[4] = 64'h4881480147814701;
RAM[5] = 64'h4a814a0149814901;
RAM[6] = 64'h4c814c014b814b01;
RAM[7] = 64'h4e814e014d814d01;
RAM[8] = 64'h0110011b4f814f01;
RAM[9] = 64'h059b45011161016e;
RAM[10] = 64'h0004063705fe0010;
RAM[11] = 64'h05a000ef8006061b;
RAM[12] = 64'h0ff003930000100f;
RAM[13] = 64'h4e952e3110012e37;
RAM[14] = 64'hc602829b0053f2b7;
RAM[15] = 64'h2023fe02dfe312fd;
RAM[16] = 64'h829b0053f2b7007e;
RAM[17] = 64'hfe02dfe312fdc602;
RAM[18] = 64'h4de31efd000e2023;
RAM[19] = 64'h059bf1402573fdd0;
RAM[20] = 64'h0000061705e20870;
RAM[21] = 64'h0010029b01260613;
RAM[22] = 64'h11010002806702fe;
RAM[23] = 64'h84b2842ae426e822;
RAM[24] = 64'h892ee04aec064505;
RAM[25] = 64'h06e000ef07e000ef;
RAM[26] = 64'h979334fd02905563;
RAM[27] = 64'h07930177d4930204;
RAM[28] = 64'h4089093394be2004;
RAM[29] = 64'h04138522008905b3;
RAM[30] = 64'h19e3014000ef2004;
RAM[31] = 64'h64a2644260e2fe94;
RAM[32] = 64'h6749808261056902;
RAM[33] = 64'hdfed8b8510472783;
RAM[34] = 64'h2423479110a73823;
RAM[35] = 64'h10472783674910f7;
RAM[36] = 64'h20058693ffed8b89;
RAM[37] = 64'h05a1118737836749;
RAM[38] = 64'hfed59be3fef5bc23;
RAM[39] = 64'h1047278367498082;
RAM[40] = 64'h67c98082dfed8b85;
RAM[41] = 64'h0000808210a7a023;
end
generate
if(`FPGA) begin
initial begin
//$readmemh(PRELOAD, RAM);
// FPGA only
RAM[0] = 64'h94e1819300002197;
RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301;
RAM[3] = 64'h4681460145814501;
RAM[4] = 64'h4881480147814701;
RAM[5] = 64'h4a814a0149814901;
RAM[6] = 64'h4c814c014b814b01;
RAM[7] = 64'h4e814e014d814d01;
RAM[8] = 64'h0110011b4f814f01;
RAM[9] = 64'h059b45011161016e;
RAM[10] = 64'h0004063705fe0010;
RAM[11] = 64'h05a000ef8006061b;
RAM[12] = 64'h0ff003930000100f;
RAM[13] = 64'h4e952e3110012e37;
RAM[14] = 64'hc602829b0053f2b7;
RAM[15] = 64'h2023fe02dfe312fd;
RAM[16] = 64'h829b0053f2b7007e;
RAM[17] = 64'hfe02dfe312fdc602;
RAM[18] = 64'h4de31efd000e2023;
RAM[19] = 64'h059bf1402573fdd0;
RAM[20] = 64'h0000061705e20870;
RAM[21] = 64'h0010029b01260613;
RAM[22] = 64'h11010002806702fe;
RAM[23] = 64'h84b2842ae426e822;
RAM[24] = 64'h892ee04aec064505;
RAM[25] = 64'h06e000ef07e000ef;
RAM[26] = 64'h979334fd02905563;
RAM[27] = 64'h07930177d4930204;
RAM[28] = 64'h4089093394be2004;
RAM[29] = 64'h04138522008905b3;
RAM[30] = 64'h19e3014000ef2004;
RAM[31] = 64'h64a2644260e2fe94;
RAM[32] = 64'h6749808261056902;
RAM[33] = 64'hdfed8b8510472783;
RAM[34] = 64'h2423479110a73823;
RAM[35] = 64'h10472783674910f7;
RAM[36] = 64'h20058693ffed8b89;
RAM[37] = 64'h05a1118737836749;
RAM[38] = 64'hfed59be3fef5bc23;
RAM[39] = 64'h1047278367498082;
RAM[40] = 64'h67c98082dfed8b85;
RAM[41] = 64'h0000808210a7a023;
end // initial begin
end // if (FPGA)
endgenerate
assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);