mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
slmnemo
commit
f413ea1b4a
@ -1 +1 @@
|
||||
Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
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||||
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
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||||
46
fpga/README.md
Normal file
46
fpga/README.md
Normal file
@ -0,0 +1,46 @@
|
||||
The FPGA currently only targets the VCU118 board.
|
||||
|
||||
* Build Process
|
||||
|
||||
cd generator
|
||||
make
|
||||
|
||||
* Description
|
||||
|
||||
The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4,
|
||||
axi_clock_converter, and ahblite_axi_bridge. Then it reads in the 4 IP blocks
|
||||
and builds wally. fpga/src/fpgaTop.v is the top level which instanciates
|
||||
wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic
|
||||
analyzer) which provides the current instruction PCM, instrM, etc along with
|
||||
a large number of debuging signals.
|
||||
|
||||
* Programming the flash card
|
||||
You'll need to write the linux image to the flash card. Use the convert2bin.py
|
||||
script in wally-pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
|
||||
file from QEMU's preload to generate the binary. Then to copy
|
||||
sudo dd if=ram.bin of=<path to flash card>.
|
||||
|
||||
* Loading the FPGA
|
||||
|
||||
After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's
|
||||
gui and open the WallyFPGA.xpr project file. Open the hardware manager under
|
||||
program and debug. Open target and then program with the bit file.
|
||||
|
||||
* Test Run
|
||||
|
||||
Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide
|
||||
status of the reset and ddr4 calibration. LED 7 should always be lit.
|
||||
LED 6 will light if the DDR4 is not calibrated. LED 6 will be lit once
|
||||
wally begins running.
|
||||
|
||||
Next the bootloader program will copy the flash card into the DDR4 memory.
|
||||
When this done the lower 5 LEDs will blink 5 times and then try to boot
|
||||
the program loaded in the DDR4 memory at physical address 0x8000_0000.
|
||||
|
||||
* Connecting uart
|
||||
You'll need to connect both usb cables. The first connects the FPGA programer
|
||||
while the connect connects UART. UART is configured to use 57600 baud with
|
||||
no parity, 8 data bits, and 1 stop bit. sudo screen /dev/ttyUSB1 57600 should
|
||||
let you view the com port.
|
||||
|
||||
|
||||
@ -282,7 +282,7 @@ set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
|
||||
|
||||
|
||||
|
||||
set_max_delay -datapath_only -from [get_pins wrapper_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins wrapper_i/proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
|
||||
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -20,68 +20,86 @@ read_verilog {../src/fpgaTop.v}
|
||||
set_property include_dirs {../../wally-pipelined/config/fpga ../../wally-pipelined/config/shared} [current_fileset]
|
||||
|
||||
# contrainsts generated by the IP blocks
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc
|
||||
#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc
|
||||
set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc
|
||||
set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc]
|
||||
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc]
|
||||
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc
|
||||
# implementation only
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc
|
||||
#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
|
||||
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc
|
||||
|
||||
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0_ooc_debug.xdc
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.runs/xlnx_ahblite_axi_bridge_synth_1/dont_touch.xdc
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.runs/xlnx_proc_sys_reset_synth_1/dont_touch.xdc
|
||||
@ -98,14 +116,13 @@ add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/
|
||||
# define top level
|
||||
set_property top fpgaTop [current_fileset]
|
||||
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
|
||||
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
update_compile_order -fileset constrs_1
|
||||
# this line is wrong vvv
|
||||
#update_compile_order -fileset constrs_1
|
||||
# This is important as the ddr4 IP contains the generate clock constraint which the user constraints depend on.
|
||||
report_compile_order -constraints > reports/compile_order.rpt
|
||||
|
||||
@ -130,6 +147,8 @@ report_utilization -hierarchical -file re
|
||||
report_cdc -file reports/cdc.rpt
|
||||
report_clock_interaction -file reports/clock_interaction.rpt
|
||||
|
||||
source ../constraints/debug2.xdc
|
||||
|
||||
|
||||
# set for RuntimeOptimized implementation
|
||||
#set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
|
||||
|
||||
@ -192,8 +192,8 @@ module fpgaTop
|
||||
|
||||
// SD Card Tristate
|
||||
IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low
|
||||
.I(SDCCmdIn),
|
||||
.O(SDCCmdOut),
|
||||
.I(SDCCmdOut),
|
||||
.O(SDCCmdIn),
|
||||
.IO(SDCCmd));
|
||||
|
||||
// reset controller XILINX IP
|
||||
|
||||
@ -1,5 +1,10 @@
|
||||
|
||||
`include "../../../config/rv64icfd/wally-config.vh"
|
||||
//`include "../../../config/old/rv64icfd/wally-config.vh"
|
||||
|
||||
`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
|
||||
`define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
|
||||
`define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
|
||||
`define XLEN 64
|
||||
module testbench3();
|
||||
|
||||
logic [31:0] errors=0;
|
||||
@ -174,8 +179,9 @@ always @(posedge clk)
|
||||
// check results on falling edge of clk
|
||||
always @(negedge clk) begin
|
||||
|
||||
// fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w");
|
||||
if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] == {XExpE,1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] == {YExpE,1'b1,Y[`NF-2:0]})) || (ZNaNE && (FMAResM[`FLEN-2:0] == {ZExpE,1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] == ans[`FLEN-2:0]))))) begin
|
||||
// fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w");
|
||||
// if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (FMAResM != ans))) begin
|
||||
$display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
|
||||
if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero ");
|
||||
if(XDenormE) $display( "xdenorm ");
|
||||
@ -193,7 +199,7 @@ always @(posedge clk)
|
||||
if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ~ans[`NF-1]) $display( "ans=sigNaN ");
|
||||
if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ans[`NF-1]) $display( "ans=qutNaN ");
|
||||
errors = errors + 1;
|
||||
|
||||
//if (errors == 10)
|
||||
$stop;
|
||||
end
|
||||
if((FmtE==1'b0)&(FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[30:0] == {X[30:23],1'b1,X[21:0]})) || (YNaNE && (FMAResM[30:0] == {Y[30:23],1'b1,Y[21:0]})) || (ZNaNE && (FMAResM[30:0] == {Z[30:23],1'b1,Z[21:0]})) || (FMAResM[30:0] == ans[30:0]))) ))) begin
|
||||
|
||||
13
wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py
Executable file
13
wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py
Executable file
@ -0,0 +1,13 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
asciiBinFile = 'ram.txt'
|
||||
binFile = 'ram.bin'
|
||||
|
||||
asciiBinFP = open(asciiBinFile, 'r')
|
||||
binFP = open (binFile, 'wb')
|
||||
|
||||
for line in asciiBinFP.readlines():
|
||||
binFP.write(int(line, 16).to_bytes(8, byteorder='little', signed=False))
|
||||
|
||||
asciiBinFP.close()
|
||||
binFP.close()
|
||||
@ -9,4 +9,6 @@ make allclean
|
||||
make
|
||||
make XLEN=32
|
||||
exe2memfile.pl work/*/*/*.elf
|
||||
cd ../../wally-pipelined/regression
|
||||
cd ../linux-testgen/linux-testvectors
|
||||
./tvLinker.sh
|
||||
cd ../../../wally-pipelined/regression
|
||||
|
||||
@ -10,9 +10,11 @@
|
||||
# output.
|
||||
#
|
||||
##################################
|
||||
import sys
|
||||
import sys,os
|
||||
|
||||
from collections import namedtuple
|
||||
regressionDir = os.path.dirname(os.path.abspath(__file__))
|
||||
os.chdir(regressionDir)
|
||||
TestCase = namedtuple("TestCase", ['name', 'cmd', 'grepstr'])
|
||||
# name: the name of this test configuration (used in printing human-readable
|
||||
# output and picking logfile names)
|
||||
@ -78,6 +80,7 @@ def run_test_case(config):
|
||||
logname = "logs/wally_"+config.name+".log"
|
||||
cmd = config.cmd.format(logname)
|
||||
print(cmd)
|
||||
os.chdir(regressionDir)
|
||||
os.system(cmd)
|
||||
if search_log_for_text(config.grepstr, logname):
|
||||
print("%s: Success" % config.name)
|
||||
@ -91,11 +94,13 @@ def main():
|
||||
"""Run the tests and count the failures"""
|
||||
global configs
|
||||
try:
|
||||
os.chdir(regressionDir)
|
||||
os.mkdir("logs")
|
||||
except:
|
||||
pass
|
||||
|
||||
if '-makeTests' in sys.argv:
|
||||
os.chdir(regressionDir)
|
||||
os.system('./make-tests.sh | tee ./logs/make-tests.log')
|
||||
|
||||
if '-all' in sys.argv:
|
||||
|
||||
@ -23,8 +23,11 @@
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
// `include "../../../config/rv64icfd/wally-config.vh"
|
||||
|
||||
// `define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
|
||||
// `define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
|
||||
// `define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
|
||||
// `define XLEN 64
|
||||
module fma(
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
@ -113,7 +116,7 @@ module fma1(
|
||||
logic [3*`NF+5:0] AlignedAddendE; // Z aligned for addition in U(NF+5.2NF+1)
|
||||
logic [3*`NF+6:0] AlignedAddendInv; // aligned addend possibly inverted
|
||||
logic [2*`NF+1:0] ProdManKilled; // the product's mantissa possibly killed
|
||||
logic [3*`NF+6:0] NegProdManKilled; // a negated ProdManKilled
|
||||
logic [3*`NF+4:0] NegProdManKilled; // a negated ProdManKilled
|
||||
logic [8:0] PNormCnt, NNormCnt; // the positive and nagitive LOA results
|
||||
logic [3*`NF+6:0] PreSum, NegPreSum; // positive and negitve versions of the sum
|
||||
|
||||
@ -149,11 +152,11 @@ module fma1(
|
||||
|
||||
add add(.AlignedAddendE, .ProdManE, .PSgnE, .ZSgnEffE, .KillProdE, .AlignedAddendInv, .ProdManKilled, .NegProdManKilled, .NegSumE, .PreSum, .NegPreSum, .InvZE, .XZeroE, .YZeroE);
|
||||
|
||||
loa loa(.AlignedAddendE, .AlignedAddendInv, .ProdManKilled, .NegProdManKilled, .PNormCnt, .NNormCnt);
|
||||
loa loa(.A(AlignedAddendInv+{162'b0,InvZE}), .P(ProdManKilled), .NegSumE, .NormCntE);
|
||||
|
||||
// Choose the positive sum and accompanying LZA result.
|
||||
assign SumE = NegSumE ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
|
||||
assign NormCntE = NegSumE ? NNormCnt : PNormCnt;
|
||||
// assign NormCntE = NegSumE ? NNormCnt : PNormCnt;
|
||||
|
||||
|
||||
endmodule
|
||||
@ -311,7 +314,7 @@ module add(
|
||||
input logic XZeroE, YZeroE, // is the input zero
|
||||
output logic [3*`NF+6:0] AlignedAddendInv, // aligned addend possibly inverted
|
||||
output logic [2*`NF+1:0] ProdManKilled, // the product's mantissa possibly killed
|
||||
output logic [3*`NF+6:0] NegProdManKilled, // a negated ProdManKilled
|
||||
output logic [3*`NF+4:0] NegProdManKilled, // a negated ProdManKilled
|
||||
output logic NegSumE, // was the sum negitive
|
||||
output logic InvZE, // do you invert Z
|
||||
output logic [3*`NF+6:0] PreSum, NegPreSum// possibly negitive sum
|
||||
@ -327,99 +330,65 @@ module add(
|
||||
assign InvZE = ZSgnEffE ^ PSgnE;
|
||||
|
||||
// Choose an inverted or non-inverted addend - the one has to be added now for the LZA
|
||||
assign AlignedAddendInv = InvZE ? -{1'b0, AlignedAddendE} : {1'b0, AlignedAddendE};
|
||||
assign AlignedAddendInv = InvZE ? {1'b1, ~AlignedAddendE} : {1'b0, AlignedAddendE};
|
||||
// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
|
||||
assign ProdManKilled = ProdManE&{2*`NF+2{~KillProdE}};
|
||||
// Negate ProdMan for LZA and the negitive sum calculation
|
||||
assign NegProdManKilled = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, -ProdManKilled, 2'b0};
|
||||
assign NegProdManKilled = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, ~ProdManKilled&{2*`NF+2{~(XZeroE|YZeroE)}}};
|
||||
|
||||
|
||||
// Is the sum negitive
|
||||
assign NegSumE = (AlignedAddendE > {54'b0, ProdManKilled, 2'b0})&InvZE; //***use this to avoid addition and final muxing???
|
||||
|
||||
// Do the addition
|
||||
// - calculate a positive and negitive sum in parallel
|
||||
assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0};
|
||||
assign NegPreSum = AlignedAddendE + NegProdManKilled;
|
||||
assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE};
|
||||
assign NegPreSum = AlignedAddendE + {NegProdManKilled, 2'b0} + {{(3*`NF+3){1'b0}},~(XZeroE|YZeroE),2'b0};
|
||||
|
||||
// Is the sum negitive
|
||||
assign NegSumE = PreSum[3*`NF+6];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module loa(
|
||||
input logic [3*`NF+5:0] AlignedAddendE, // Z aligned for addition in U(NF+5.2NF+1)
|
||||
input logic [3*`NF+6:0] AlignedAddendInv, // aligned addend possibly inverted
|
||||
input logic [2*`NF+1:0] ProdManKilled, // the product's mantissa possibly killed
|
||||
input logic [3*`NF+6:0] NegProdManKilled, // a negated ProdManKilled
|
||||
output logic [8:0] PNormCnt, NNormCnt // positive and negitive LOA result
|
||||
);
|
||||
|
||||
// LZAs one for the positive result and one for the negitive
|
||||
// - the +1 from inverting causes problems for normalization
|
||||
posloa posloa(AlignedAddendInv, ProdManKilled, PNormCnt);
|
||||
negloa negloa({1'b0,AlignedAddendE}, NegProdManKilled, NNormCnt);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module posloa(
|
||||
module loa( //https://ieeexplore.ieee.org/abstract/document/930098
|
||||
input logic [3*`NF+6:0] A, // addend
|
||||
input logic [2*`NF+1:0] P, // product
|
||||
output logic [8:0] PCnt // normalization shift count for the positive result
|
||||
input logic NegSumE, // is the sum negitive
|
||||
output logic [8:0] NormCntE // normalization shift count for the positive result
|
||||
);
|
||||
|
||||
|
||||
// calculate the propagate (T) and kill (Z) bits
|
||||
logic [3*`NF+6:0] T;
|
||||
logic [3*`NF+5:0] G;
|
||||
logic [3*`NF+5:0] Z;
|
||||
assign T[3*`NF+6:2*`NF+4] = A[3*`NF+6:2*`NF+4];
|
||||
assign Z[3*`NF+5:2*`NF+4] = A[3*`NF+5:2*`NF+4];
|
||||
assign G[3*`NF+5:2*`NF+4] = 0;
|
||||
assign Z[3*`NF+5:2*`NF+4] = ~A[3*`NF+5:2*`NF+4];
|
||||
assign T[2*`NF+3:2] = A[2*`NF+3:2]^P;
|
||||
assign Z[2*`NF+3:2] = A[2*`NF+3:2]|P;
|
||||
assign G[2*`NF+3:2] = A[2*`NF+3:2]&P;
|
||||
assign Z[2*`NF+3:2] = ~A[2*`NF+3:2]&~P;
|
||||
assign T[1:0] = A[1:0];
|
||||
assign Z[1:0] = A[1:0];
|
||||
assign G[1:0] = 0;
|
||||
assign Z[1:0] = ~A[1:0];
|
||||
|
||||
|
||||
// Apply function to determine Leading pattern
|
||||
logic [3*`NF+6:0] f;
|
||||
assign f = T^{Z[3*`NF+5:0], 1'b0};
|
||||
assign f = NegSumE ? T^{~G[3*`NF+5:0],1'b1} : T^{~Z[3*`NF+5:0], 1'b1};
|
||||
|
||||
lzc lzc(.f, .Cnt(PCnt));
|
||||
lzc lzc(.f, .NormCntE);
|
||||
|
||||
endmodule
|
||||
|
||||
module negloa(
|
||||
input logic [3*`NF+6:0] A, // addend
|
||||
input logic [3*`NF+6:0] P, // product
|
||||
output logic [8:0] NCnt // normalization shift count for the negitive result
|
||||
);
|
||||
|
||||
// calculate the propagate (T) and kill (Z) bits
|
||||
logic [3*`NF+6:0] T;
|
||||
logic [3*`NF+5:0] Z;
|
||||
assign T = A^P;
|
||||
assign Z = ~(A[3*`NF+5:0]|P[3*`NF+5:0]);
|
||||
|
||||
|
||||
// Apply function to determine Leading pattern
|
||||
logic [3*`NF+6:0] f;
|
||||
assign f = T^{~Z, 1'b0};
|
||||
|
||||
lzc lzc(.f, .Cnt(NCnt));
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module lzc(
|
||||
input logic [3*`NF+6:0] f,
|
||||
output logic [8:0] Cnt // normalization shift count for the negitive result
|
||||
output logic [8:0] NormCntE // normalization shift
|
||||
);
|
||||
|
||||
logic [8:0] i;
|
||||
always_comb begin
|
||||
i = 0;
|
||||
while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one
|
||||
Cnt = i;
|
||||
NormCntE = i;
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -479,7 +448,7 @@ module fma2(
|
||||
// Normalization
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum,
|
||||
normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum, .NegSumM,
|
||||
.SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm);
|
||||
|
||||
|
||||
@ -611,6 +580,80 @@ module resultselect(
|
||||
endmodule
|
||||
|
||||
|
||||
// module normalize(
|
||||
// input logic [3*`NF+5:0] SumM, // the positive sum
|
||||
// input logic [`NE-1:0] ZExpM, // exponent of Z
|
||||
// input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
|
||||
// input logic [8:0] NormCntM, // normalization shift count
|
||||
// input logic FmtM, // precision 1 = double 0 = single
|
||||
// input logic KillProdM, // is the product set to zero
|
||||
// input logic AddendStickyM, // the sticky bit caclulated from the aligned addend
|
||||
// input logic NegSumM, // was the sum negitive
|
||||
// output logic [`NF+2:0] NormSum, // normalized sum
|
||||
// output logic SumZero, // is the sum zero
|
||||
// output logic NormSumSticky, UfSticky, // sticky bits
|
||||
// output logic [`NE+1:0] SumExp, // exponent of the normalized sum
|
||||
// output logic ResultDenorm // is the result denormalized
|
||||
// );
|
||||
// logic [`NE+1:0] FracLen; // length of the fraction
|
||||
// logic [`NE+1:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results
|
||||
// logic [8:0] DenormShift; // right shift if the result is denormalized //***change this later
|
||||
// logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction
|
||||
// logic [3*`NF+7:0] SumShifted; // the shifted sum before LZA correction
|
||||
// logic [`NE+1:0] SumExpTmpTmp; // the exponent of the normalized sum with the `FLEN bias
|
||||
// logic PreResultDenorm; // is the result denormalized - calculated before LZA corection
|
||||
// logic PreResultDenorm2; // is the result denormalized - calculated before LZA corection
|
||||
// logic LZAPlus1; // add one to the sum's exponent due to LZA correction
|
||||
|
||||
// ///////////////////////////////////////////////////////////////////////////////
|
||||
// // Normalization
|
||||
// ///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// // Determine if the sum is zero
|
||||
// assign SumZero = ~(|SumM);
|
||||
|
||||
// // determine the length of the fraction based on precision
|
||||
// assign FracLen = FmtM ? `NF+1 : 13'd24;
|
||||
|
||||
// // calculate the sum's exponent
|
||||
// assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); // ****try moving this into previous stage
|
||||
// assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}}; // ***move this ^ the subtraction by a constant isn't simplified
|
||||
|
||||
// logic SumDLTEZ, SumDGEFL, SumSLTEZ, SumSGEFL;
|
||||
// assign SumDLTEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp;
|
||||
// assign SumDGEFL = ($signed(SumExpTmpTmp)>=$signed(-(13'd`NF+13'd1)));
|
||||
// assign SumSLTEZ = $signed(SumExpTmpTmp) <= $signed(13'd1023-13'd127);
|
||||
// assign SumSGEFL = ($signed(SumExpTmpTmp)>=$signed(-13'd24+13'd1023-13'd127)) | ~|SumExpTmpTmp;
|
||||
// assign PreResultDenorm2 = (FmtM ? SumDLTEZ : SumSLTEZ) & (FmtM ? SumDGEFL : SumSGEFL) & ~SumZero; //***make sure math good
|
||||
// // always_comb begin
|
||||
// // assert (PreResultDenorm == PreResultDenorm2) else $fatal ("PreResultDenorms not equal");
|
||||
// // end
|
||||
|
||||
|
||||
|
||||
// // Determine if the result is denormal
|
||||
// // assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
|
||||
|
||||
// // Determine the shift needed for denormal results
|
||||
// // - if not denorm add 1 to shift out the leading 1
|
||||
// assign DenormShift = PreResultDenorm2 ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
|
||||
// // Normalize the sum
|
||||
// assign SumShifted = {2'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
|
||||
// // LZA correction
|
||||
// assign LZAPlus1 = SumShifted[3*`NF+7];
|
||||
// assign CorrSumShifted = LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0];
|
||||
// assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3];
|
||||
// // Calculate the sticky bit
|
||||
// assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | (|CorrSumShifted[136:2*`NF+3]&~FmtM);
|
||||
// assign UfSticky = AddendStickyM | NormSumSticky;
|
||||
|
||||
// // Determine sum's exponent
|
||||
// assign SumExp = (SumExpTmp+{12'b0, LZAPlus1}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]}) & {`NE+2{~(SumZero|ResultDenorm)}};
|
||||
// // recalculate if the result is denormalized
|
||||
// assign ResultDenorm = PreResultDenorm2&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
|
||||
|
||||
// endmodule
|
||||
|
||||
module normalize(
|
||||
input logic [3*`NF+5:0] SumM, // the positive sum
|
||||
input logic [`NE-1:0] ZExpM, // exponent of Z
|
||||
@ -619,6 +662,7 @@ module normalize(
|
||||
input logic FmtM, // precision 1 = double 0 = single
|
||||
input logic KillProdM, // is the product set to zero
|
||||
input logic AddendStickyM, // the sticky bit caclulated from the aligned addend
|
||||
input logic NegSumM, // was the sum negitive
|
||||
output logic [`NF+2:0] NormSum, // normalized sum
|
||||
output logic SumZero, // is the sum zero
|
||||
output logic NormSumSticky, UfSticky, // sticky bits
|
||||
@ -629,15 +673,29 @@ module normalize(
|
||||
logic [`NE+1:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results
|
||||
logic [8:0] DenormShift; // right shift if the result is denormalized //***change this later
|
||||
logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction
|
||||
logic [3*`NF+7:0] SumShifted; // the shifted sum before LZA correction
|
||||
logic [3*`NF+8:0] SumShifted; // the shifted sum before LZA correction
|
||||
logic [`NE+1:0] SumExpTmpTmp; // the exponent of the normalized sum with the `FLEN bias
|
||||
logic PreResultDenorm; // is the result denormalized - calculated before LZA corection
|
||||
logic LZAPlus1; // add one to the sum's exponent due to LZA correction
|
||||
logic PreResultDenorm2; // is the result denormalized - calculated before LZA corection
|
||||
logic LZAPlus1, LZAPlus2; // add one or two to the sum's exponent due to LZA correction
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Normalization
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// logic [8:0] supposedNormCnt;
|
||||
// logic [8:0] i;
|
||||
// always_comb begin
|
||||
// i = 0;
|
||||
// while (~SumM[3*`NF+5-i] && $unsigned(i) <= $unsigned(3*`NF+5)) i = i+1; // search for leading one
|
||||
// supposedNormCnt = i; // compute shift count
|
||||
// end
|
||||
|
||||
// always_comb begin
|
||||
// assert (NormCntM == supposedNormCnt | NormCntM == supposedNormCnt+1 | NormCntM == supposedNormCnt+2) else $fatal ("normcnt not expected");
|
||||
// end
|
||||
|
||||
// Determine if the sum is zero
|
||||
assign SumZero = ~(|SumM);
|
||||
|
||||
@ -645,19 +703,36 @@ module normalize(
|
||||
assign FracLen = FmtM ? `NF+1 : 13'd24;
|
||||
|
||||
// calculate the sum's exponent
|
||||
assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4));
|
||||
assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}};
|
||||
assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); // ****try moving this into previous stage
|
||||
assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}}; // ***move this ^ the subtraction by a constant isn't simplified
|
||||
|
||||
logic SumDLTEZ, SumDGEFL, SumSLTEZ, SumSGEFL;
|
||||
assign SumDLTEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp;
|
||||
assign SumDGEFL = ($signed(SumExpTmpTmp)>=$signed(-(13'd`NF+13'd1)));
|
||||
assign SumSLTEZ = $signed(SumExpTmpTmp) <= $signed(13'd1023-13'd127);
|
||||
assign SumSGEFL = ($signed(SumExpTmpTmp)>=$signed(-13'd24+13'd1023-13'd127)) | ~|SumExpTmpTmp;
|
||||
assign PreResultDenorm2 = (FmtM ? SumDLTEZ : SumSLTEZ) & (FmtM ? SumDGEFL : SumSGEFL) & ~SumZero; //***make sure math good
|
||||
// always_comb begin
|
||||
// assert (PreResultDenorm == PreResultDenorm2) else $fatal ("PreResultDenorms not equal");
|
||||
// end
|
||||
|
||||
// 010. when should be 001.
|
||||
// - shift left one
|
||||
// - add one from exp
|
||||
// - if kill prod dont add to exp
|
||||
|
||||
// Determine if the result is denormal
|
||||
assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
|
||||
// assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
|
||||
|
||||
// Determine the shift needed for denormal results
|
||||
// - if not denorm add 1 to shift out the leading 1
|
||||
assign DenormShift = PreResultDenorm ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
|
||||
assign DenormShift = PreResultDenorm2 ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
|
||||
// Normalize the sum
|
||||
assign SumShifted = {2'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
|
||||
assign SumShifted = {3'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
|
||||
// LZA correction
|
||||
assign LZAPlus1 = SumShifted[3*`NF+7];
|
||||
assign LZAPlus2 = SumShifted[3*`NF+8];
|
||||
// the only possible mantissa for a plus two is all zeroes - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
|
||||
assign CorrSumShifted = LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0];
|
||||
assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3];
|
||||
// Calculate the sticky bit
|
||||
@ -665,9 +740,10 @@ module normalize(
|
||||
assign UfSticky = AddendStickyM | NormSumSticky;
|
||||
|
||||
// Determine sum's exponent
|
||||
assign SumExp = (SumExpTmp+{12'b0, LZAPlus1}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]}) & {`NE+2{~(SumZero|ResultDenorm)}};
|
||||
// if plus1 If plus2 if said denorm but norm plus 1 if said denorm (-1 val) but norm plus 2
|
||||
assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}+{11'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM, 1'b0}) & {`NE+2{~(SumZero|ResultDenorm)}};
|
||||
// recalculate if the result is denormalized
|
||||
assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
|
||||
assign ResultDenorm = PreResultDenorm2&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -96,7 +96,7 @@ module datapath (
|
||||
//Mux for writting floating point
|
||||
|
||||
regfile regf(clk, reset, {RegWriteW | FWriteIntW}, Rs1D, Rs2D, RdW, WriteDataW, RD1D, RD2D);
|
||||
extend ext(.InstrD(InstrD[31:7]), .*);
|
||||
extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
|
||||
|
||||
// Execute stage pipeline register and logic
|
||||
flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, RD1D, RD1E);
|
||||
|
||||
@ -90,9 +90,69 @@ module ieu (
|
||||
logic MemReadE, CSRReadE;
|
||||
logic JumpE;
|
||||
|
||||
controller c(.*);
|
||||
datapath dp(.*);
|
||||
forward fw(.*);
|
||||
controller c(
|
||||
.clk, .reset,
|
||||
// Decode stage control signals
|
||||
.StallD, .FlushD, .InstrD, .ImmSrcD,
|
||||
.IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
|
||||
// Execute stage control signals
|
||||
.StallE, .FlushE, .FlagsE,
|
||||
.PCSrcE, // for datapath and Hazard Unit
|
||||
.ALUControlE, .ALUSrcAE, .ALUSrcBE,
|
||||
.TargetSrcE,
|
||||
.MemReadE, .CSRReadE, // for Hazard Unit
|
||||
.Funct3E, .MulDivE, .W64E,
|
||||
.JumpE,
|
||||
// Memory stage control signals
|
||||
.StallM, .FlushM, .MemRWM,
|
||||
.CSRReadM, .CSRWriteM, .PrivilegedM,
|
||||
.SCE, .AtomicE, .AtomicM, .Funct3M,
|
||||
.RegWriteM, // for Hazard Unit
|
||||
.InvalidateICacheM, .FlushDCacheM, .InstrValidM,
|
||||
// Writeback stage control signals
|
||||
.StallW, .FlushW,
|
||||
.RegWriteW, // for datapath and Hazard Unit
|
||||
.ResultSrcW,
|
||||
// Stall during CSRs
|
||||
.CSRWritePendingDEM,
|
||||
.StoreStallD
|
||||
);
|
||||
|
||||
datapath dp(
|
||||
.clk, .reset,
|
||||
// Decode stage signals
|
||||
.ImmSrcD, .InstrD,
|
||||
// Execute stage signals
|
||||
.StallE, .FlushE, .ForwardAE, .ForwardBE,
|
||||
.ALUControlE, .ALUSrcAE, .ALUSrcBE,
|
||||
.TargetSrcE, .JumpE, .IllegalFPUInstrE,
|
||||
.FWriteDataE, .PCE, .PCLinkE, .FlagsE,
|
||||
.PCTargetE,
|
||||
.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||
.SrcAE, .SrcBE,
|
||||
// Memory stage signals
|
||||
.StallM, .FlushM, .FWriteIntM, .FIntResM,
|
||||
.SrcAM, .WriteDataM, .MemAdrM, .MemAdrE,
|
||||
// Writeback stage signals
|
||||
.StallW, .FlushW, .FWriteIntW, .RegWriteW,
|
||||
.SquashSCW, .ResultSrcW, .ReadDataW,
|
||||
// input logic [`XLEN-1:0] PCLinkW,
|
||||
.CSRReadValW, .ReadDataM, .MulDivResultW,
|
||||
// Hazard Unit signals
|
||||
.Rs1D, .Rs2D, .Rs1E, .Rs2E,
|
||||
.RdE, .RdM, .RdW
|
||||
);
|
||||
|
||||
forward fw(
|
||||
.Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
|
||||
.MemReadE, .MulDivE, .CSRReadE,
|
||||
.RegWriteM, .RegWriteW,
|
||||
.FWriteIntE, .FWriteIntM, .FWriteIntW,
|
||||
.SCE,
|
||||
// Forwarding controls
|
||||
.ForwardAE, .ForwardBE,
|
||||
.FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -64,7 +64,6 @@ module sd_dat_fsm
|
||||
(* mark_debug = "true" *) logic [3:0] r_curr_state;
|
||||
logic [3:0] w_next_state;
|
||||
|
||||
(* mark_debug = "true" *) logic w_error_crc16_fd_en, w_error_crc16_fd_rst, w_error_crc16_fd_d; // Save ERROR_CRC16 so CMD FSM sees it in IDLE_NRC (not just in IDLE_DAT)
|
||||
logic r_error_crc16_fd_Q;
|
||||
|
||||
logic [22:0] Identify_Timer_In;
|
||||
|
||||
@ -49,54 +49,56 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
|
||||
logic memwrite;
|
||||
logic [3:0] busycount;
|
||||
|
||||
initial begin
|
||||
//$readmemh(PRELOAD, RAM);
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
// FPGA only
|
||||
RAM[0] = 64'h94e1819300002197;
|
||||
RAM[1] = 64'h4281420141014081;
|
||||
RAM[2] = 64'h4481440143814301;
|
||||
RAM[3] = 64'h4681460145814501;
|
||||
RAM[4] = 64'h4881480147814701;
|
||||
RAM[5] = 64'h4a814a0149814901;
|
||||
RAM[6] = 64'h4c814c014b814b01;
|
||||
RAM[7] = 64'h4e814e014d814d01;
|
||||
RAM[8] = 64'h0110011b4f814f01;
|
||||
RAM[9] = 64'h059b45011161016e;
|
||||
RAM[10] = 64'h0004063705fe0010;
|
||||
RAM[11] = 64'h05a000ef8006061b;
|
||||
RAM[12] = 64'h0ff003930000100f;
|
||||
RAM[13] = 64'h4e952e3110012e37;
|
||||
RAM[14] = 64'hc602829b0053f2b7;
|
||||
RAM[15] = 64'h2023fe02dfe312fd;
|
||||
RAM[16] = 64'h829b0053f2b7007e;
|
||||
RAM[17] = 64'hfe02dfe312fdc602;
|
||||
RAM[18] = 64'h4de31efd000e2023;
|
||||
RAM[19] = 64'h059bf1402573fdd0;
|
||||
RAM[20] = 64'h0000061705e20870;
|
||||
RAM[21] = 64'h0010029b01260613;
|
||||
RAM[22] = 64'h11010002806702fe;
|
||||
RAM[23] = 64'h84b2842ae426e822;
|
||||
RAM[24] = 64'h892ee04aec064505;
|
||||
RAM[25] = 64'h06e000ef07e000ef;
|
||||
RAM[26] = 64'h979334fd02905563;
|
||||
RAM[27] = 64'h07930177d4930204;
|
||||
RAM[28] = 64'h4089093394be2004;
|
||||
RAM[29] = 64'h04138522008905b3;
|
||||
RAM[30] = 64'h19e3014000ef2004;
|
||||
RAM[31] = 64'h64a2644260e2fe94;
|
||||
RAM[32] = 64'h6749808261056902;
|
||||
RAM[33] = 64'hdfed8b8510472783;
|
||||
RAM[34] = 64'h2423479110a73823;
|
||||
RAM[35] = 64'h10472783674910f7;
|
||||
RAM[36] = 64'h20058693ffed8b89;
|
||||
RAM[37] = 64'h05a1118737836749;
|
||||
RAM[38] = 64'hfed59be3fef5bc23;
|
||||
RAM[39] = 64'h1047278367498082;
|
||||
RAM[40] = 64'h67c98082dfed8b85;
|
||||
RAM[41] = 64'h0000808210a7a023;
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
end
|
||||
generate
|
||||
if(`FPGA) begin
|
||||
initial begin
|
||||
//$readmemh(PRELOAD, RAM);
|
||||
// FPGA only
|
||||
RAM[0] = 64'h94e1819300002197;
|
||||
RAM[1] = 64'h4281420141014081;
|
||||
RAM[2] = 64'h4481440143814301;
|
||||
RAM[3] = 64'h4681460145814501;
|
||||
RAM[4] = 64'h4881480147814701;
|
||||
RAM[5] = 64'h4a814a0149814901;
|
||||
RAM[6] = 64'h4c814c014b814b01;
|
||||
RAM[7] = 64'h4e814e014d814d01;
|
||||
RAM[8] = 64'h0110011b4f814f01;
|
||||
RAM[9] = 64'h059b45011161016e;
|
||||
RAM[10] = 64'h0004063705fe0010;
|
||||
RAM[11] = 64'h05a000ef8006061b;
|
||||
RAM[12] = 64'h0ff003930000100f;
|
||||
RAM[13] = 64'h4e952e3110012e37;
|
||||
RAM[14] = 64'hc602829b0053f2b7;
|
||||
RAM[15] = 64'h2023fe02dfe312fd;
|
||||
RAM[16] = 64'h829b0053f2b7007e;
|
||||
RAM[17] = 64'hfe02dfe312fdc602;
|
||||
RAM[18] = 64'h4de31efd000e2023;
|
||||
RAM[19] = 64'h059bf1402573fdd0;
|
||||
RAM[20] = 64'h0000061705e20870;
|
||||
RAM[21] = 64'h0010029b01260613;
|
||||
RAM[22] = 64'h11010002806702fe;
|
||||
RAM[23] = 64'h84b2842ae426e822;
|
||||
RAM[24] = 64'h892ee04aec064505;
|
||||
RAM[25] = 64'h06e000ef07e000ef;
|
||||
RAM[26] = 64'h979334fd02905563;
|
||||
RAM[27] = 64'h07930177d4930204;
|
||||
RAM[28] = 64'h4089093394be2004;
|
||||
RAM[29] = 64'h04138522008905b3;
|
||||
RAM[30] = 64'h19e3014000ef2004;
|
||||
RAM[31] = 64'h64a2644260e2fe94;
|
||||
RAM[32] = 64'h6749808261056902;
|
||||
RAM[33] = 64'hdfed8b8510472783;
|
||||
RAM[34] = 64'h2423479110a73823;
|
||||
RAM[35] = 64'h10472783674910f7;
|
||||
RAM[36] = 64'h20058693ffed8b89;
|
||||
RAM[37] = 64'h05a1118737836749;
|
||||
RAM[38] = 64'hfed59be3fef5bc23;
|
||||
RAM[39] = 64'h1047278367498082;
|
||||
RAM[40] = 64'h67c98082dfed8b85;
|
||||
RAM[41] = 64'h0000808210a7a023;
|
||||
end // initial begin
|
||||
end // if (FPGA)
|
||||
endgenerate
|
||||
|
||||
assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);
|
||||
|
||||
|
||||
@ -48,7 +48,7 @@ module testbench();
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// HARDWARE ///////////////////////////////////
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
logic clk, reset, reset_ext;
|
||||
logic clk, reset_ext;
|
||||
initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
|
||||
always begin clk <= 1; # 5; clk <= 0; # 5; end
|
||||
|
||||
@ -85,6 +85,9 @@ module testbench();
|
||||
.UARTSin, .UARTSout,
|
||||
.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
|
||||
|
||||
logic reset;
|
||||
assign reset = dut.reset;
|
||||
|
||||
// Write Back stage signals not needed by Wally itself
|
||||
parameter nop = 'h13;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user