mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
bbracker
commit
302bc56646
46
fpga/README.md
Normal file
46
fpga/README.md
Normal file
@ -0,0 +1,46 @@
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||||
The FPGA currently only targets the VCU118 board.
|
||||
|
||||
* Build Process
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||||
|
||||
cd generator
|
||||
make
|
||||
|
||||
* Description
|
||||
|
||||
The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4,
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||||
axi_clock_converter, and ahblite_axi_bridge. Then it reads in the 4 IP blocks
|
||||
and builds wally. fpga/src/fpgaTop.v is the top level which instanciates
|
||||
wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic
|
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analyzer) which provides the current instruction PCM, instrM, etc along with
|
||||
a large number of debuging signals.
|
||||
|
||||
* Programming the flash card
|
||||
You'll need to write the linux image to the flash card. Use the convert2bin.py
|
||||
script in wally-pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
|
||||
file from QEMU's preload to generate the binary. Then to copy
|
||||
sudo dd if=ram.bin of=<path to flash card>.
|
||||
|
||||
* Loading the FPGA
|
||||
|
||||
After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's
|
||||
gui and open the WallyFPGA.xpr project file. Open the hardware manager under
|
||||
program and debug. Open target and then program with the bit file.
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||||
|
||||
* Test Run
|
||||
|
||||
Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide
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||||
status of the reset and ddr4 calibration. LED 7 should always be lit.
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||||
LED 6 will light if the DDR4 is not calibrated. LED 6 will be lit once
|
||||
wally begins running.
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||||
|
||||
Next the bootloader program will copy the flash card into the DDR4 memory.
|
||||
When this done the lower 5 LEDs will blink 5 times and then try to boot
|
||||
the program loaded in the DDR4 memory at physical address 0x8000_0000.
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||||
|
||||
* Connecting uart
|
||||
You'll need to connect both usb cables. The first connects the FPGA programer
|
||||
while the connect connects UART. UART is configured to use 57600 baud with
|
||||
no parity, 8 data bits, and 1 stop bit. sudo screen /dev/ttyUSB1 57600 should
|
||||
let you view the com port.
|
||||
|
||||
|
||||
@ -282,7 +282,7 @@ set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
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||||
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||||
|
||||
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||||
set_max_delay -datapath_only -from [get_pins wrapper_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins wrapper_i/proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
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||||
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
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||||
|
||||
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
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||||
|
||||
File diff suppressed because one or more lines are too long
@ -20,68 +20,86 @@ read_verilog {../src/fpgaTop.v}
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||||
set_property include_dirs {../../wally-pipelined/config/fpga ../../wally-pipelined/config/shared} [current_fileset]
|
||||
|
||||
# contrainsts generated by the IP blocks
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc]
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||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc]
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc]
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||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc
|
||||
#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc]
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc
|
||||
set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc
|
||||
set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc]
|
||||
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc]
|
||||
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc
|
||||
# implementation only
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc
|
||||
#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
|
||||
|
||||
|
||||
add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc
|
||||
|
||||
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0_ooc_debug.xdc
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.runs/xlnx_ahblite_axi_bridge_synth_1/dont_touch.xdc
|
||||
|
||||
#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.runs/xlnx_proc_sys_reset_synth_1/dont_touch.xdc
|
||||
@ -98,14 +116,13 @@ add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/
|
||||
# define top level
|
||||
set_property top fpgaTop [current_fileset]
|
||||
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
|
||||
#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
|
||||
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
update_compile_order -fileset constrs_1
|
||||
# this line is wrong vvv
|
||||
#update_compile_order -fileset constrs_1
|
||||
# This is important as the ddr4 IP contains the generate clock constraint which the user constraints depend on.
|
||||
report_compile_order -constraints > reports/compile_order.rpt
|
||||
|
||||
@ -130,6 +147,8 @@ report_utilization -hierarchical -file re
|
||||
report_cdc -file reports/cdc.rpt
|
||||
report_clock_interaction -file reports/clock_interaction.rpt
|
||||
|
||||
source ../constraints/debug2.xdc
|
||||
|
||||
|
||||
# set for RuntimeOptimized implementation
|
||||
#set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
|
||||
|
||||
@ -192,8 +192,8 @@ module fpgaTop
|
||||
|
||||
// SD Card Tristate
|
||||
IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low
|
||||
.I(SDCCmdIn),
|
||||
.O(SDCCmdOut),
|
||||
.I(SDCCmdOut),
|
||||
.O(SDCCmdIn),
|
||||
.IO(SDCCmd));
|
||||
|
||||
// reset controller XILINX IP
|
||||
|
||||
13
wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py
Executable file
13
wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py
Executable file
@ -0,0 +1,13 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
asciiBinFile = 'ram.txt'
|
||||
binFile = 'ram.bin'
|
||||
|
||||
asciiBinFP = open(asciiBinFile, 'r')
|
||||
binFP = open (binFile, 'wb')
|
||||
|
||||
for line in asciiBinFP.readlines():
|
||||
binFP.write(int(line, 16).to_bytes(8, byteorder='little', signed=False))
|
||||
|
||||
asciiBinFP.close()
|
||||
binFP.close()
|
||||
@ -64,7 +64,6 @@ module sd_dat_fsm
|
||||
(* mark_debug = "true" *) logic [3:0] r_curr_state;
|
||||
logic [3:0] w_next_state;
|
||||
|
||||
(* mark_debug = "true" *) logic w_error_crc16_fd_en, w_error_crc16_fd_rst, w_error_crc16_fd_d; // Save ERROR_CRC16 so CMD FSM sees it in IDLE_NRC (not just in IDLE_DAT)
|
||||
logic r_error_crc16_fd_Q;
|
||||
|
||||
logic [22:0] Identify_Timer_In;
|
||||
|
||||
@ -49,54 +49,56 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
|
||||
logic memwrite;
|
||||
logic [3:0] busycount;
|
||||
|
||||
initial begin
|
||||
//$readmemh(PRELOAD, RAM);
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
// FPGA only
|
||||
RAM[0] = 64'h94e1819300002197;
|
||||
RAM[1] = 64'h4281420141014081;
|
||||
RAM[2] = 64'h4481440143814301;
|
||||
RAM[3] = 64'h4681460145814501;
|
||||
RAM[4] = 64'h4881480147814701;
|
||||
RAM[5] = 64'h4a814a0149814901;
|
||||
RAM[6] = 64'h4c814c014b814b01;
|
||||
RAM[7] = 64'h4e814e014d814d01;
|
||||
RAM[8] = 64'h0110011b4f814f01;
|
||||
RAM[9] = 64'h059b45011161016e;
|
||||
RAM[10] = 64'h0004063705fe0010;
|
||||
RAM[11] = 64'h05a000ef8006061b;
|
||||
RAM[12] = 64'h0ff003930000100f;
|
||||
RAM[13] = 64'h4e952e3110012e37;
|
||||
RAM[14] = 64'hc602829b0053f2b7;
|
||||
RAM[15] = 64'h2023fe02dfe312fd;
|
||||
RAM[16] = 64'h829b0053f2b7007e;
|
||||
RAM[17] = 64'hfe02dfe312fdc602;
|
||||
RAM[18] = 64'h4de31efd000e2023;
|
||||
RAM[19] = 64'h059bf1402573fdd0;
|
||||
RAM[20] = 64'h0000061705e20870;
|
||||
RAM[21] = 64'h0010029b01260613;
|
||||
RAM[22] = 64'h11010002806702fe;
|
||||
RAM[23] = 64'h84b2842ae426e822;
|
||||
RAM[24] = 64'h892ee04aec064505;
|
||||
RAM[25] = 64'h06e000ef07e000ef;
|
||||
RAM[26] = 64'h979334fd02905563;
|
||||
RAM[27] = 64'h07930177d4930204;
|
||||
RAM[28] = 64'h4089093394be2004;
|
||||
RAM[29] = 64'h04138522008905b3;
|
||||
RAM[30] = 64'h19e3014000ef2004;
|
||||
RAM[31] = 64'h64a2644260e2fe94;
|
||||
RAM[32] = 64'h6749808261056902;
|
||||
RAM[33] = 64'hdfed8b8510472783;
|
||||
RAM[34] = 64'h2423479110a73823;
|
||||
RAM[35] = 64'h10472783674910f7;
|
||||
RAM[36] = 64'h20058693ffed8b89;
|
||||
RAM[37] = 64'h05a1118737836749;
|
||||
RAM[38] = 64'hfed59be3fef5bc23;
|
||||
RAM[39] = 64'h1047278367498082;
|
||||
RAM[40] = 64'h67c98082dfed8b85;
|
||||
RAM[41] = 64'h0000808210a7a023;
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
end
|
||||
generate
|
||||
if(`FPGA) begin
|
||||
initial begin
|
||||
//$readmemh(PRELOAD, RAM);
|
||||
// FPGA only
|
||||
RAM[0] = 64'h94e1819300002197;
|
||||
RAM[1] = 64'h4281420141014081;
|
||||
RAM[2] = 64'h4481440143814301;
|
||||
RAM[3] = 64'h4681460145814501;
|
||||
RAM[4] = 64'h4881480147814701;
|
||||
RAM[5] = 64'h4a814a0149814901;
|
||||
RAM[6] = 64'h4c814c014b814b01;
|
||||
RAM[7] = 64'h4e814e014d814d01;
|
||||
RAM[8] = 64'h0110011b4f814f01;
|
||||
RAM[9] = 64'h059b45011161016e;
|
||||
RAM[10] = 64'h0004063705fe0010;
|
||||
RAM[11] = 64'h05a000ef8006061b;
|
||||
RAM[12] = 64'h0ff003930000100f;
|
||||
RAM[13] = 64'h4e952e3110012e37;
|
||||
RAM[14] = 64'hc602829b0053f2b7;
|
||||
RAM[15] = 64'h2023fe02dfe312fd;
|
||||
RAM[16] = 64'h829b0053f2b7007e;
|
||||
RAM[17] = 64'hfe02dfe312fdc602;
|
||||
RAM[18] = 64'h4de31efd000e2023;
|
||||
RAM[19] = 64'h059bf1402573fdd0;
|
||||
RAM[20] = 64'h0000061705e20870;
|
||||
RAM[21] = 64'h0010029b01260613;
|
||||
RAM[22] = 64'h11010002806702fe;
|
||||
RAM[23] = 64'h84b2842ae426e822;
|
||||
RAM[24] = 64'h892ee04aec064505;
|
||||
RAM[25] = 64'h06e000ef07e000ef;
|
||||
RAM[26] = 64'h979334fd02905563;
|
||||
RAM[27] = 64'h07930177d4930204;
|
||||
RAM[28] = 64'h4089093394be2004;
|
||||
RAM[29] = 64'h04138522008905b3;
|
||||
RAM[30] = 64'h19e3014000ef2004;
|
||||
RAM[31] = 64'h64a2644260e2fe94;
|
||||
RAM[32] = 64'h6749808261056902;
|
||||
RAM[33] = 64'hdfed8b8510472783;
|
||||
RAM[34] = 64'h2423479110a73823;
|
||||
RAM[35] = 64'h10472783674910f7;
|
||||
RAM[36] = 64'h20058693ffed8b89;
|
||||
RAM[37] = 64'h05a1118737836749;
|
||||
RAM[38] = 64'hfed59be3fef5bc23;
|
||||
RAM[39] = 64'h1047278367498082;
|
||||
RAM[40] = 64'h67c98082dfed8b85;
|
||||
RAM[41] = 64'h0000808210a7a023;
|
||||
end // initial begin
|
||||
end // if (FPGA)
|
||||
endgenerate
|
||||
|
||||
assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user