David Harris
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b911056e66
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Changed Wally to CORE-V Wally
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2023-01-11 14:03:44 -08:00 |
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David Harris
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e92cffbb5e
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Changed MIT license to Solderpad License
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2023-01-10 11:35:20 -08:00 |
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Ross Thompson
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b5a85b55f1
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
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2022-12-23 15:10:37 -06:00 |
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David Harris
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93bb8036be
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Revert to 98b824
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2022-12-22 23:58:14 -08:00 |
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David Harris
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567f76c2a5
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Code cleanup
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2022-12-22 10:04:50 -08:00 |
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David Harris
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0c10ec942a
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Replaced || and && with single ops
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2022-12-20 01:33:35 -08:00 |
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David Harris
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940fd2f924
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Clean up interrupt masking by Commit
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2022-12-16 08:27:39 -08:00 |
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Ross Thompson
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fbf543bf57
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Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
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2022-11-29 17:19:31 -06:00 |
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Ross Thompson
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0ed0c18aa1
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Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
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2022-10-02 16:21:21 -05:00 |
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Ross Thompson
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32449dfe97
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Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
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2022-09-28 17:39:51 -05:00 |
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David Harris
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31815422d2
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../src/privileged/csrc.sv
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2022-05-31 21:12:17 +00:00 |
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David Harris
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2935188035
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Moved delegation logic from privmode to trap to simplify interface
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2022-05-31 14:58:11 +00:00 |
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David Harris
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f5e2cff45a
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Cause simplification
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2022-05-12 23:47:21 +00:00 |
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David Harris
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6303d4e81f
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Cause simplification
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2022-05-12 23:39:10 +00:00 |
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David Harris
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de51c7eeb3
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Cause simplification
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2022-05-12 23:33:22 +00:00 |
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David Harris
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87dadc8208
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trap/csr cleanup
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2022-05-12 22:26:21 +00:00 |
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David Harris
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ea0d9fd9a8
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More trap/csr simplification
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2022-05-12 22:06:03 +00:00 |
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David Harris
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2eb6a65fa2
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More trap/csr simplification
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2022-05-12 22:04:20 +00:00 |
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David Harris
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2d8ccbd4ea
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More trap/csr simplification
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2022-05-12 22:00:23 +00:00 |
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David Harris
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417e36bff5
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More trap/csr simplification
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2022-05-12 21:55:50 +00:00 |
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David Harris
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ca6b7716e2
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Simplifying trap/csr interface
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2022-05-12 21:50:15 +00:00 |
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David Harris
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56c154f2e7
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Simplified MTVAL logic
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2022-05-12 21:36:13 +00:00 |
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David Harris
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5537c33196
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Formatting cleanup
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2022-05-12 18:37:47 +00:00 |
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David Harris
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5acb526375
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More unused signal cleanup
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2022-05-12 15:21:09 +00:00 |
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David Harris
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7e764fbda1
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More unused signal cleanup
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2022-05-12 15:15:30 +00:00 |
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David Harris
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e2dea3bb89
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Removed more unused signals, simplified csri state
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2022-05-12 15:10:10 +00:00 |
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David Harris
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fb725a9e0a
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Clean up unused signals
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2022-05-12 14:49:58 +00:00 |
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David Harris
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8066ba45e8
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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David Harris
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2792d77e4e
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Fixed bug in delegated interrupts not being taken
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2022-05-08 04:50:27 +00:00 |
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David Harris
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2cdd49c7d2
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WFI terminates when an interrupt is pending even if interrupts are globally disabled
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2022-05-08 04:30:46 +00:00 |
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David Harris
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16ad1e0cab
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Fixed InstrMisalignedFaultM mtval
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2022-04-24 17:31:30 +00:00 |
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David Harris
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f1ddbb169c
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Improved priority order and mtval of traps to match spec
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2022-04-24 17:24:45 +00:00 |
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Kip Macsai-Goren
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7bc6943527
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
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David Harris
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2436534687
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First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
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Ross Thompson
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2294cbc1c6
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Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
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2022-04-07 16:56:28 -05:00 |
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bbracker
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54b9745a75
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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David Harris
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049c55769a
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fpu compare simplification, minor cleanup
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2022-03-29 17:11:28 +00:00 |
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Kip Macsai-Goren
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dc9635b757
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fixed double multiplication on vectored interrupts
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2022-03-28 19:12:31 +00:00 |
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David Harris
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aa990be959
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removed csrn and all of its outputs because depricated
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2022-02-15 19:59:29 +00:00 |
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David Harris
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d8170e9dd3
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Mostly removed N_SUPPORTED
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2022-02-15 19:50:44 +00:00 |
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David Harris
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ed8ac3d881
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Just needed to recompile - all good. Now removed uretM because N-mode is depricated
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2022-02-15 19:48:49 +00:00 |
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Ross Thompson
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7fedc6b878
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Cleaned up the InstrMisalignedFault.
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2022-01-28 13:19:24 -06:00 |
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Ross Thompson
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1bb8d36308
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Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
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2022-01-27 17:11:27 -06:00 |
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Ross Thompson
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000d713cb5
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Better solution to the integer divider interrupt interaction.
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2022-01-12 14:22:18 -06:00 |
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Ross Thompson
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48c036a923
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Oups. My hack for DivE interrupt prevention was wrong.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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796316495d
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Hack "fix" to prevent interrupt from occuring during an integer divide.
This is not the desired solution but will allow continued debuging of linux.
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2022-01-12 14:17:16 -06:00 |
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David Harris
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3d2671a8b0
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Reformatted MIT license to 95 characters
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2022-01-07 12:58:40 +00:00 |
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David Harris
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d66f7c841b
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Removed generate statements
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2022-01-05 14:35:25 +00:00 |
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David Harris
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115287adc8
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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