65 Commits

Author	SHA1	Message	Date
Shreya Sanghai	d9b1e7d67f	added gshare and global history predictor	2021-03-16 17:03:01 -04:00
Shreya Sanghai	a79e26f9d8	added global history branch predictor	2021-03-16 16:06:40 -04:00
Shreya Sanghai	518618ad38	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Ross Thompson	8e51935082	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
David Harris	bea8ac6d59	WALLY-LRSC atomic test passing	2021-03-09 09:28:25 -05:00
Shreya Sanghai	7cd8f1a592	added performance counters	2021-03-04 11:42:52 -05:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	9511dcac84	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	9530039e3d	Implemented adrdec for uncore	2021-01-29 17:28:53 -05:00
David Harris	e4e95bf941	Added ahblite bus interface unit	2021-01-29 01:07:17 -05:00
David Harris	4318629b32	Repartitioned datapath and controller into ieu	2021-01-27 06:40:26 -05:00
David Harris	b7988e536f	Reset Vector moved to config file	2021-01-25 15:57:36 -05:00
David Harris	bf07ec92b5	Added test configurations	2021-01-25 11:28:43 -05:00