Ross Thompson
165a36acac
Modified wally-pipelined.do for no trace linux sim.
2022-04-21 09:52:33 -05:00
David Harris
861fbd698b
Run 4M instructions in buildroot test to get through kernel & VirtMem startup
2022-04-18 01:29:38 +00:00
David Harris
83d283354c
Added comments in fcvt
2022-04-17 16:53:10 +00:00
Ross Thompson
238cc9f9fd
Commented output power analysis to speed simulation.
2022-04-16 15:32:59 -05:00
Ross Thompson
f995ec2a54
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-10 13:41:27 -05:00
Ross Thompson
c3d9eafe60
Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
2022-04-10 13:27:54 -05:00
bbracker
3b6cb5f0ba
small signs of life on new interrupt spoofing
2022-04-08 12:32:30 -07:00
David Harris
c22d6f2848
Added bootmem source ccode
2022-04-05 23:22:53 +00:00
Ross Thompson
d83db2cde5
Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
2022-04-04 09:57:26 -05:00
Ross Thompson
e7abcd862f
fpga simulation works again.
2022-04-03 17:31:07 -05:00
Kip Macsai-Goren
cdea062287
added RV64IA config to have a config without compressed instructions
2022-04-02 18:24:08 +00:00
Ross Thompson
987236e463
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-01 17:18:25 -05:00
Ross Thompson
57eba4355e
Updated the fpga test bench.
2022-04-01 17:14:47 -05:00
bbracker
cbff9a7755
expand WALLY-PERIPH test to use SEIP on PLIC context 1
2022-03-31 18:02:06 -07:00
Kip Macsai-Goren
2e68ab7bb4
added test config that doesn't use compressed instructions for privileged tests
2022-03-28 19:12:31 +00:00
Skylar Litz
29d1f64588
add AtemptedInstructionCount signal
2022-03-26 21:28:57 +00:00
Skylar Litz
bb8587e06f
update to match new filesystem organization
2022-03-26 21:28:32 +00:00
bbracker
efb5d1dbc0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-04 00:06:27 +00:00
bbracker
443dd40ea8
remove imperas32p tests
2022-03-04 00:06:18 +00:00
David Harris
545f569f78
Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
2022-03-03 15:38:08 +00:00
bbracker
e28ca531e0
fix peripheral test and add it to regression
2022-03-02 23:44:39 +00:00
bbracker
c1290d493f
add CSRs to waveview
2022-03-02 18:31:10 +00:00
bbracker
d7b8c9d877
add rv32a tests to regression
2022-03-02 17:54:55 +00:00
bbracker
5f5cc514b8
fix buildroot checkpointing and add it back to regression
2022-03-02 16:00:19 +00:00
bbracker
4f22a55dd4
add LRSC test and add wally64a to regression
2022-03-02 07:09:37 +00:00
bbracker
41b3912abc
buildroot graphical sim bugfix
2022-03-01 03:24:23 +00:00
bbracker
04ace8c154
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
2022-03-01 03:11:43 +00:00
bbracker
d620fb4442
deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
2022-03-01 00:37:46 +00:00
David Harris
046259cff8
Moved regression work directories to regression/wkdir to reduce clutter
2022-02-27 17:35:09 +00:00
David Harris
eb0bbacd43
Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue
2022-02-27 15:12:10 +00:00
David Harris
eda60a7691
Moved Softfloat / TestFloat
2022-02-26 19:17:32 +00:00
Ross Thompson
d331b9f29d
Fixed "bug" with wally-pipelined.do
2022-02-22 22:19:25 -06:00
bbracker
6caa97bb26
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
Ross Thompson
ad237b3ce5
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
0eec096474
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
Ross Thompson
2fc7dc3e57
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
eafd52e2bc
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Skylar Litz
0c69d3291d
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
Ross Thompson
a440bc2ac5
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
b1cba4be2b
Updates to linux wave.
2022-02-11 13:28:18 -06:00
Ross Thompson
9145a96b53
Updated linux wave.
2022-02-11 13:15:42 -06:00
Ross Thompson
3f4ae91468
linux wave cleanup.
2022-02-11 10:48:45 -06:00
Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
Ross Thompson
9ad4523b9d
Updated wave files to reflect recent changes.
2022-02-10 17:52:19 -06:00
Ross Thompson
327a05c9d8
Added commented out commands to generate saif file from vsim.
2022-02-09 18:40:45 -06:00
David Harris
096242a6d8
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
David Harris
72c2166223
Lab 3 file cleanup
2022-02-08 10:26:37 +00:00
David Harris
d0c40cca7a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-07 14:43:31 +00:00
David Harris
0feb624bab
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
bbracker
fc2e3d1fbf
remove rv32e from regression because it is broken; goes with previous commit
2022-02-05 23:05:21 +00:00
David Harris
0dd8c719ad
Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
2022-02-05 05:35:51 +00:00
David Harris
f7d6939d9b
Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts
2022-02-05 05:28:40 +00:00
David Harris
581fbb7d13
Modified wally-pipelined-batch.do to handle buildroot
2022-02-05 05:07:07 +00:00
David Harris
23868a33bc
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
David Harris
16b5fee795
RV32e tests
2022-02-04 14:30:36 +00:00
David Harris
1c049f1f67
renamed configs
2022-02-03 23:36:41 +00:00
David Harris
e92461159d
cache cleanup
2022-02-03 15:36:11 +00:00
Ross Thompson
4a5aa43716
Merge branch 'makefiles' into main
2022-02-03 08:33:50 -06:00
Ross Thompson
55382be055
Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the
...
regression directory. Makefile calls the submakefiles for generating elf files.
The second makefile-memfiles generates the memfiles, addr, and label files.
2022-02-03 08:32:48 -06:00
Ross Thompson
9da3223ce6
Manged to get all the tests compiled and converted to memfiles using new makefiles.
2022-02-03 00:00:15 -06:00
Ross Thompson
41978d59e4
Quick patch to regression-wally to "fix" rv32ic.
2022-02-02 19:24:24 -06:00
Ross Thompson
789cf13be6
broken makefiles.
2022-02-02 19:15:11 -06:00
Ross Thompson
ac19cd48a4
Broken makefiles.
2022-02-02 19:14:42 -06:00
David Harris
9e0055cbb9
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
Ross Thompson
f3c2e426b1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-02 11:41:54 -06:00
David Harris
761dae72fe
Config file & wally-riscv-arch-test cleanup
2022-02-02 16:35:52 +00:00
Ross Thompson
88a408b3e6
Added helpful signals to wavefile.
...
Makefile for tests now creates the function address to name mapping files.
The function name and test name are included in the wave file.
2022-02-02 10:15:54 -06:00
Ross Thompson
2d8b0aa650
Modified makefiles to generate function address to name mappings for modelsim.
2022-02-01 18:25:03 -06:00
Ross Thompson
058b368a22
Improved function_radix to not printout warnings when no valid function is found.
2022-02-01 18:03:09 -06:00
Ross Thompson
138b17a399
Setup the main regression test to be able to handle coremark.
2022-02-01 17:00:11 -06:00
Ross Thompson
d2ab17e1af
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
3475e142a5
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
de0bef4f5b
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
1bb8d36308
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
d38ab9d2d7
Increased number of concurrent tests.
2022-01-27 08:45:25 -06:00
Ross Thompson
b961b104e0
Added colors to regression script to make it easy to pick out success from fail.
2022-01-26 22:40:32 -06:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
0bb63e9ad1
Fixed path to riscvOVPsimPlus
2022-01-21 00:12:14 +00:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
0d0aa59e48
Removed imperas tests from makefile for now
2022-01-20 14:51:56 +00:00
David Harris
f420e63ed0
Added top-level make clean
2022-01-20 14:17:26 +00:00
David Harris
1a21e7f011
riscvsingle reparittioned to match Ch4
2022-01-17 16:57:32 +00:00
David Harris
de7b9c127e
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
b967bcede2
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
f7f3882cb8
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
ce937a35a8
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
Ross Thompson
5726b5b640
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
861450c4d6
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
87485f9f64
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
David Harris
4cae11ad28
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
467aac8463
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
55456e465c
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
e01c8bc5f6
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
3109fa1383
Fixed wavefile.
...
Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
David Harris
89ee6c778e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
Ross Thompson
b6ae6fea27
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
573ff47763
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
6fafabbfad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
53637049b7
Makefile make allclean
2022-01-06 23:04:30 +00:00
Katherine Parry
631d05dcdc
some FPU test fixes
2022-01-06 23:03:20 +00:00
David Harris
8305eb80ff
Restored many of the arch32f and arch64d that had been failing because of memfile issues
2022-01-05 22:23:46 +00:00
David Harris
90dd961ea5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-05 22:10:33 +00:00
David Harris
07932ad0aa
Replaced exe2memfile with SiFive elf2hex
2022-01-05 22:10:26 +00:00
Ross Thompson
0310df96a4
Changes to wave file.
2022-01-05 14:16:59 -06:00
David Harris
d66f7c841b
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
888a60d8d6
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
David Harris
9ddc6db0a6
Removed imperas mmu tests; using wallypriv instead
2022-01-04 23:14:53 +00:00
David Harris
d1a7416028
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
