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slack-notifier
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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wave-dos
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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buildrootBugFinder.py
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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fpga-wave.do
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cache cleanup
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2022-02-03 15:36:11 +00:00 |
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lint-wally
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Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
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2022-02-06 01:22:40 +00:00 |
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linux-wave.do
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cache cleanup
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2022-02-03 15:36:11 +00:00 |
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make-tests.sh
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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Makefile
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Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the
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2022-02-03 08:32:48 -06:00 |
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makefile-memfile
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Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the
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2022-02-03 08:32:48 -06:00 |
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regression-wally
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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sim-buildroot
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Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts
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2022-02-05 05:28:40 +00:00 |
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sim-buildroot-batch
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Modified wally-pipelined-batch.do to handle buildroot
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2022-02-05 05:07:07 +00:00 |
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sim-coremark-batch
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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sim-fp64
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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sim-fp64-batch
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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sim-wally
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Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
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2022-02-05 04:16:18 +00:00 |
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sim-wally-batch
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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wally-coremark.do
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Improve wavefile by adding performance counters.
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2022-01-12 10:53:29 -06:00 |
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wally-fp64-batch.do
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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wally-fp64.do
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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wally-harvard.do
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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wally-pipelined-batch.do
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Modified wally-pipelined-batch.do to handle buildroot
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2022-02-05 05:07:07 +00:00 |
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wally-pipelined-fpga.do
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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wally-pipelined.do
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Added commented out commands to generate saif file from vsim.
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2022-02-09 18:40:45 -06:00 |
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wave-all.do
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Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
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2022-01-27 17:11:27 -06:00 |
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wave-coremark.do
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cache cleanup
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2022-02-03 15:36:11 +00:00 |
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wave.do
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cache cleanup
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2022-02-03 15:36:11 +00:00 |
