Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-01 17:34:27 +00:00
Code Issues Packages Projects Releases Wiki Activity
4,776 Commits 4 Branches 2 Tags 53 MiB
8ca6c1255e
Commit Graph

1833 Commits

Author SHA1 Message Date
David Harris
0ecbb45b78 Fixed register timing failure on SpecialCaseM in fdivsqrt 2022-12-29 21:09:23 -08:00
Ross Thompson
5d844801d2 Fixed problems with changes to ram2p. 2022-12-29 17:13:48 -06:00
Ross Thompson
a76ea1c6aa Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-29 17:07:53 -06:00
Ross Thompson
31ec70029e Re-enabled the branch predictor in rv64gc. 2022-12-29 17:07:50 -06:00
Katherine Parry
e5a76817df minor optimizations and renaming 2022-12-29 15:54:17 -06:00
Katherine Parry
a8021d7571 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-29 12:37:51 -06:00
David Harris
963185fb22 Clean up names and comments in divsqrt 2022-12-29 08:02:44 -08:00
David Harris
103c4b8324 Factored out hardware unique to RV64 and to IDIV 2022-12-29 07:36:26 -08:00
Katherine Parry
b469831b53 one bitt removed from inital lignment shift 2022-12-28 17:46:53 -06:00
Alessandro Maiuolo
aa1201561e added script in pipelined folder to run regressions with all radix/copies configurations 2022-12-28 07:32:35 -08:00
David Harris
a9d7aa568a fdivsqrtfsm conditional on IDIV (fixed typo) 2022-12-27 22:16:48 -08:00
David Harris
5b7e814670 fdivsqrtfsm conditional on IDIV 2022-12-27 22:15:45 -08:00
David Harris
4648fbee76 fdivsqrtfsm conditional on IDIV 2022-12-27 22:14:09 -08:00
Cedar Turek
42d2ca1556 idiv passing radix 2, four copies 2022-12-27 22:11:18 -08:00
Cedar Turek
6d933a88c7 idiv passing radix 2, four copies 2022-12-27 22:10:48 -08:00
David Harris
f16a15e66f Moved IDIV in fdivsqrtfms into generate block 2022-12-27 22:04:50 -08:00
David Harris
3975fd5ed8 Moved IDIV for postproc into generate block 2022-12-27 22:02:14 -08:00
David Harris
62c01d865a Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc 2022-12-27 21:53:00 -08:00
Cedar Turek
00073155c5 Fixed cycles for multiple iterations. 2-copies radix 2 passing regression. 2022-12-27 21:34:27 -08:00
David Harris
17bd0d9d68 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-27 21:30:13 -08:00
David Harris
0a0ca0ae07 cleanup 2022-12-27 21:29:36 -08:00
David Harris
d6aad0f3c3 Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
David Harris
20787964c9 Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
Ross Thompson
5d91434b32 signal name changes in ram2p. 2022-12-27 15:07:01 -06:00
Ross Thompson
2c0f3d2c6c Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-27 15:06:25 -06:00
Ross Thompson
1f42098758 Added about moving decompressed config generate. 2022-12-27 15:04:55 -06:00
David Harris
9544051c1e Removed MDUE from unnecessary places in fdivsqrt 2022-12-27 10:42:40 -08:00
David Harris
c903f8b8b2 fdiv typo 2022-12-27 10:30:42 -08:00
David Harris
ed26850439 Made SqrtE only true on square root so gating with ~MDUE can be removed) 2022-12-27 10:27:07 -08:00
David Harris
f5cc23cae9 Check for non-negative W in int sign handling 2022-12-27 06:35:17 -08:00
Cedar Turek
d41b07aa85 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
Cedar Turek
21b2ea9666 fpu passing idiv tests on rv32gc 1 copy of radix 2! 2022-12-26 21:47:56 -08:00
Cedar Turek
6977b7ceac took out otfc swap. updated postprocessing quotient/remainder logic for int div. 2022-12-26 21:03:56 -08:00
David Harris
add381a09e Fixed early termination for square root 2022-12-26 08:54:57 -08:00
David Harris
71f214df20 Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
David Harris
3eafd2cca1 Removed unused DivSE from FPU 2022-12-26 07:29:19 -08:00
David Harris
214ef40b1c Moved floating-point tests earlier in Wally config 2022-12-25 22:31:20 -08:00
David Harris
0a067d342f Restored missing floating point load/store tests 2022-12-25 22:28:14 -08:00
David Harris
1a7c7a36d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-25 20:12:55 -08:00
Ross Thompson
1d11ff6153 Added missing assignment for no branch predictor mode. 2022-12-24 17:08:29 -06:00
David Harris
ac4797aac4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-24 12:24:38 -08:00
Ross Thompson
b14b71c7a9 Fixed bug with the performance counters not updating. 2022-12-24 14:24:17 -06:00
David Harris
921b5582da ALU cleanup 2022-12-24 07:18:35 -08:00
cturek
ba3aca413c Added A Sign register. Fixed postprocessing logic for postinc and rem calculation. 2022-12-24 06:46:52 +00:00
Ross Thompson
693f32973f Minor optimizations. 2022-12-23 20:11:36 -06:00
Ross Thompson
424012ce97 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-23 19:51:23 -06:00
Katherine Parry
66510f38af reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
f4f68cdd19 Improved comment. 2022-12-23 15:13:15 -06:00
Ross Thompson
b5a85b55f1 Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
c9c83ca5ae Removed XEnE, YEnE, and ZEnE from forward logic. 
Cleanup comments.
 2022-12-23 14:27:03 -06:00
Ross Thompson
deee433d07 Cleanup floating point hazard logic. 2022-12-23 14:21:47 -06:00
Ross Thompson
c8a0e7685a DON'T USE. First commit in attempt to move fpustall detection into the decode stage. 2022-12-23 12:47:18 -06:00
Ross Thompson
b1aa370ff1 Removed ZForwardEnE and replaced with ZEnE. 
Similar for YForwardEnE.
 2022-12-23 12:27:51 -06:00
Ross Thompson
30dd86d146 Removed unnecessary stall when MatchDE was driven 1 by RdE == 0. 2022-12-23 11:45:42 -06:00
David Harris
98ecd9c77d Commented out fdiv early termination - broke fsqrt test 2022-12-23 00:58:55 -08:00
David Harris
04dd3e5144 Fixed early termination on fdivsqrt 2022-12-23 00:53:55 -08:00
David Harris
1f6dc62bb3 Moved InstrValidNotFLushed to csr including InstrValidM 2022-12-23 00:27:44 -08:00
David Harris
85d0b697bf Removed unused StallW from CSRs 2022-12-23 00:21:36 -08:00
David Harris
fe5b9081d9 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
93bb8036be Revert to 98b824 2022-12-22 23:58:14 -08:00
David Harris
a185f563f2 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
David Harris
74979cdc82 FDIV merge 2022-12-22 23:03:03 -08:00
David Harris
51b92285d3 Removed unused signals in FPU and CSR 2022-12-22 22:59:05 -08:00
Ross Thompson
b6b30533e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-22 22:51:33 -06:00
Ross Thompson
6b105bd217 Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
5a9e94048a The LSU is properly using FlushW rather than TrapM. 2022-12-22 21:47:34 -06:00
Ross Thompson
ce7e1073fa Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
Ross Thompson
677f6f8737 Partial cleanup for BP. 2022-12-22 20:33:38 -06:00
Ross Thompson
942acb354e Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Ross Thompson
7a0b3d4fc6 Wavefile updates. 2022-12-22 19:45:02 -06:00
Kip Macsai-Goren
d25d699800 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Ross Thompson
47d61984ad First pass at resolving ifu flush on trap rather than FlushD. 2022-12-22 15:53:06 -06:00
David Harris
567f76c2a5 Code cleanup 2022-12-22 10:04:50 -08:00
cturek
04bc787647 Added negative-result int diviison support in U and UM registers. 13 tests pass! 2022-12-22 16:25:37 +00:00
cturek
1712e69c73 Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
cturek
fa03275cca Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-22 05:45:00 +00:00
cturek
c7d0c8823f Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc. 2022-12-22 05:44:55 +00:00
David Harris
4f7d9eee95 XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 20:39:38 -08:00
Ross Thompson
b3ff4fe02e CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled. 2022-12-21 22:13:05 -06:00
cturek
c405dcf0cb worked out some bugs with int div cycles 2022-12-22 02:22:01 +00:00
cturek
e441f90b32 Renamed signals to E and M stages, forwarded preprocessed n to fsm 2022-12-22 00:43:27 +00:00
Ross Thompson
d1aa5ba890 Updated cache fsm names to match book. 2022-12-21 16:49:53 -06:00
Ross Thompson
de161c675c Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-21 16:13:09 -06:00
Ross Thompson
0cb2cf9a5b Changed GatedStallF to GatedStallD. 2022-12-21 16:12:55 -06:00
David Harris
16c8655161 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 14:12:25 -08:00
David Harris
a5dc09c97f Added assertion about atomics needing caches 2022-12-21 13:57:28 -08:00
cturek
2c58fd42db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 20:41:38 +00:00
David Harris
3562542728 comment cleanup 2022-12-21 12:39:09 -08:00
David Harris
ca949f2110 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
cturek
14d9118802 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 19:35:57 +00:00
cturek
6761101645 fixed normshift calculations 2022-12-21 19:35:47 +00:00
David Harris
998f446e3c git push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-12-21 11:31:27 -08:00
David Harris
820e1ab510 Removed unused FPU signals 2022-12-21 11:31:22 -08:00
Ross Thompson
f6393d1288 Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
Ross Thompson
2b1e9f8bed The optimzied PC+2/4 logic still hanges on wally32priv. 2022-12-21 09:19:34 -06:00
Ross Thompson
a2329c8e9d Renamed PCPlusUpperF to PCPlus4F. 2022-12-21 09:18:30 -06:00
Ross Thompson
a6ffb4cef3 Added timeout check to testbench. 
A watchdog checks the value of PCW.  If it does not change within 1M cycles immediately stop simulation and report an error.
 2022-12-21 09:18:00 -06:00
Ross Thompson
3fc121ef70 Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 
Switched to even simplier PC+2/4 logic.
 2022-12-21 09:00:09 -06:00
Ross Thompson
968e174d68 Changes to wave file. 2022-12-21 08:41:47 -06:00