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627 Commits 4 Branches 2 Tags 53 MiB
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81 Commits

Author SHA1 Message Date
Thomas Fleming
f9e071baf8 Temporarily disable rv64 mmu test 
Will restore once cache revamp is pushed
 2021-04-22 13:19:18 -04:00
Domenico Ottolia
82320033d5 Add tests for stval and mtval 2021-04-21 02:31:32 -04:00
Domenico Ottolia
fed42ffe19 Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file 2021-04-21 01:12:55 -04:00
Domenico Ottolia
d5f86fadac Add tests for sepc register 2021-04-20 23:50:53 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
8c4cfa5f69 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
bbracker
0c85b1c201 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
c8c87bd0d8 merge testbench 2021-04-08 14:28:01 -04:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Domenico Ottolia
9b82fbff5a Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
bbdd4e1467 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
James E. Stine
82cd900b65 Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58 Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
31ad619a21 Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Shreya Sanghai
a79e26f9d8 added global history branch predictor 2021-03-16 16:06:40 -04:00
Ross Thompson
8e51935082 Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Ross Thompson
0edaa625e3 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
Ross Thompson
ccaaa829ce Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
David Harris
4465854423 Drafted rv32a tests 2021-03-12 00:06:23 -05:00
David Harris
d4e84c58ed 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Ross Thompson
b1d1f3995c Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Ross Thompson
f1f7884e10 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2 Added debug option to disable the function radix if not needed. 
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
 2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb I finally think I got the function radix debugger working across both 32 and 64 bit applications. 2021-03-10 14:43:44 -06:00
Ross Thompson
7b7cacbaf0 Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand. 2021-03-10 11:00:51 -06:00
David Harris
bea8ac6d59 WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Noah Boorstin
f0a103687e Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
Noah Boorstin
cfcd7d1518 busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
bbracker
7852d866ef JALR testing 2021-03-04 10:37:30 -05:00
David Harris
6f4e8b723e Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Ross Thompson
6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6 Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
David Harris
73920282af Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00