David Harris
874d5f6cce
Updated ImperasDV config to fix issue #1031
2024-10-28 15:55:34 -07:00
Zain2050
d22988b678
also added Zcd
2024-10-26 09:17:34 -07:00
Zain2050
3ba9295060
enabled Zcf in rv32gc
2024-10-26 09:06:01 -07:00
David Harris
e618596e52
Added CSR coverage
2024-10-26 02:11:40 -07:00
Corey Hickson
885d8cb936
Enabling D and ZfhD Coverage
2024-10-24 04:53:41 -07:00
David Harris
b848a1abfe
added no_pseudo_inst to only print regular instructions.
2024-10-22 05:26:29 -07:00
David Harris
aaa2edac18
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-10-16 13:26:51 -07:00
David Harris
01805d9fb1
Corrected RV32gc imperas configuration
2024-10-16 13:26:20 -07:00
David Harris
69898f65da
Disabled some features in imperasdv not implemented by Wally
2024-10-15 09:09:42 -07:00
Mysterio-Abdullah
da35944dce
Configuring Zcb
2024-10-13 17:41:59 -07:00
Corey Hickson
91299e3ce4
added Zfh coverage for rv{32/64}gc
2024-10-10 12:58:17 -07:00
David Harris
1924140f52
Added Zca coverage for RV32GC
2024-09-22 19:25:28 -07:00
David Harris
42400db9e2
Simplified per-config coverage statements
2024-09-14 19:33:29 -07:00
Jordan Carlin
ae593ed81d
Merge branch 'main' of https://github.com/openhwgroup/cvw into imperas_verbose
2024-09-10 16:10:05 -07:00
David Harris
f36eb6f73d
Added support for RV64GC coverage and fixed regression so that --fcov doesn't send --lockstep flag to wsim, which messed up wsim
2024-09-07 12:05:48 -07:00
David Harris
de26b7b6a7
Per config coverage initially working with RV32M in rv32gc config
2024-09-07 07:00:52 -07:00
David Harris
92c305ca3b
Starting to define per-config coverage
2024-09-07 06:26:54 -07:00
David Harris
ecb444697c
Starting to define per-config coverage
2024-09-07 06:14:50 -07:00
David Harris
6e0b0487dd
Recreated coverage changes
2024-09-05 16:32:45 -07:00
Jordan Carlin
9e98c834f1
Add lockstepverbose flag
2024-08-30 12:32:41 -07:00
David Harris
26f3c2a607
Added lockstep support for RV32. Not all wally privileged tests pass yet
2024-08-29 10:44:37 -07:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
bf397f791f
Change all SUPPORTED type localparamters to one bit logic. Update configs for consistency.
2024-05-14 16:24:26 -07:00
Jordan Carlin
1065b8977a
Fix Q_SUPPORTED on derived configs
2024-05-14 11:49:54 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
...
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
77137f0f60
ZAAMO and ZALRSC implemented but not tested
2024-05-07 16:45:49 -07:00
KelvinTr
01c45ab9d7
Fixed K extension changes
2024-02-28 17:05:08 -06:00
James E. Stine
171da97fe3
add config for K extensions (7 so far)
2024-02-22 12:12:56 -06:00
Rose Thompson
da65928f04
Fixed issue with branch deriv configs.
2024-02-06 16:07:41 -06:00
David Harris
bf7e20e846
IEEE754 derivatives for testfloat
2024-01-30 09:49:27 -08:00
David Harris
f37c7bb1f6
Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this
2024-01-30 06:27:18 -08:00
David Harris
32c102d89a
All deriv tests generated, use sim/make deriv
2024-01-29 14:34:42 -08:00
David Harris
9260d3c424
Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test
2024-01-18 22:46:07 -08:00
David Harris
da4eca4854
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
2024-01-15 13:24:57 -08:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
David Harris
dc3284049c
Rolled back B extension in rv32/64gc MISA because imperasDV isn't matching
2023-12-21 11:03:50 -08:00
David Harris
09ea6e6485
Set B in MISA for rv32gc and rv64gc
2023-12-20 16:29:31 -08:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
...
Progress towards verilator support.
2023-12-18 12:50:49 -06:00
David Harris
b692c913c4
Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile
2023-11-18 20:56:50 -08:00
David Harris
acc2db256f
turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep
2023-11-17 20:25:24 -08:00
Rose Thompson
fdb75203cb
Added cbop to to rv32gc.
2023-11-14 10:55:22 -06:00
Rose Thompson
95fc5f4a1c
Towards removing the FPGA config file.
2023-11-13 17:20:26 -06:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
Rose Thompson
657409aec5
Addec ZICCLSM to config files and started on lsu instance.
2023-10-27 13:07:23 -05:00
naichewa
0ff9ce527d
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
David Harris
1a6e57f8c0
Renamed wally-config to config in many comments
2023-10-16 13:49:09 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
28752303be
Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
2023-10-04 12:28:12 -07:00
Ross Thompson
f863cbf366
Actually fixed non-power of 2 issue with RAS.
...
Added RAS swapping to branch predictor scripts and configurations.
2023-09-27 12:25:05 -05:00
Ross Thompson
95c653e7df
Fixes the bpred-sim.py to support command line parameterization of the branch predictor while using the new parameterization. This is definitely a hack, but I don't see a better way.
2023-09-15 14:05:26 -05:00
