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	Disabled some features in imperasdv not implemented by Wally
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				@ -59,6 +59,24 @@
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#--override cpu/instret_undefined=T
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#--override cpu/hpmcounter_undefined=T
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# context registers not implemented
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--override cpu/scontext_undefined=T
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--override cpu/mcontext_undefined=T
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# nonratified mnosie register not implemented
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--override cpu/mnoise_undefined=T
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# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
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#--override cpu/ecode_mask=0x8000000F  # for RV32
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--override cpu/ecode_mask=0x800000000000000F # for RV64
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# Debug mode not yet supported
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--override cpu/debug_mode=none
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# Zkr entropy source and seed register not supported.
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--override cpu/Zkr=F
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--override cpu/reset_address=0x80000000
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--override cpu/unaligned=F  # Zicclsm (should be true)
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@ -57,15 +57,23 @@
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#--override cpu/instret_undefined=T
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#--override cpu/hpmcounter_undefined=T
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# context registers not implemented
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--override cpu/scontext_undefined=T
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--override cpu/mcontext_undefined=T
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# nonratified mnosie register not implemented
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--override cpu/mnoise_undefined=T
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# *** how to override other undefined registers: seed, mphmevent, mseccfg, debugger registers
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#--override cpu/seed_undefined=T
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#--override mhpmevent3_undefined=T
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#--override cpu/mseccfg_undefined=T
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#--override cpu/tselect_undefined=T
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#--override cpu/tdata1_undefined=T
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# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
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#--override cpu/ecode_mask=0x8000000F  # for RV32
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--override cpu/ecode_mask=0x800000000000000F # for RV64
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# Debug mode not yet supported
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--override cpu/debug_mode=none
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# Zkr entropy source and seed register not supported.
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--override cpu/Zkr=F
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--override cpu/reset_address=0x80000000
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