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9,609 Commits 4 Branches 2 Tags 53 MiB
869860bc55
Commit Graph

415 Commits

Author SHA1 Message Date
Rose Thompson
869860bc55 Merge branch 'main' of github.com:ross144/cvw 2024-09-02 14:08:48 -07:00
Rose Thompson
9471ccd2fc Updated Makefiles and source files to build the zsbl according to the config. 2024-09-02 14:03:47 -07:00
Rose Thompson
2e55f1cecc Well on the way to a fully automated FPGA build process which 
correctly sets the clocks and memory locations.
 2024-09-02 11:19:02 -07:00
Jacob Pease
4b8d35bd8a Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-30 14:18:54 -05:00
Jacob Pease
4acac08320 Fixed Arty constraints and corrected typos. 2024-08-30 14:17:37 -05:00
Rose Thompson
f1d9e18dee Modified fpga config to support two fpga boards with different amount of memory. 
Modified vcu108 constraints to better constrain the spi clock and in/out.
 2024-08-29 16:12:58 -07:00
Rose Thompson
0ce4d1b452 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-29 10:50:27 -07:00
Rose Thompson
7e16ddd859 Improved fpga synth script. 2024-08-27 15:50:05 -07:00
Rose Thompson
e5d3462a90 Converted wall.tcl to entirely project mode. 2024-08-27 14:15:58 -07:00
Jacob Pease
44ece7cb96 Added CVW header to spitest files. 2024-08-27 14:28:49 -05:00
Rose Thompson
f20a1564fa Added SPI debugger. 2024-08-26 17:22:13 -07:00
Jacob Pease
d649473ec8 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-24 21:57:44 -05:00
Jacob Pease
ad6734eb6d Improved the speed of the bootloader by 60s. CRC16 is now calculated with a table and a byte is now sent for every byte read, keeping the FIFO full. 2024-08-24 21:36:29 -05:00
Rose Thompson
ee1e09a6a2 VCU108 now boot linux at 50MHz! 2024-08-23 17:18:47 -07:00
Rose Thompson
14083bc642 VCU108 is not synthesizing at 50MHz. Still running into a few problems 
with the new SPI sd card device.
 2024-08-23 16:17:15 -07:00
Rose Thompson
842aea157c Updated vc108 constraints for spi based sd card and setting 50 Mhz. 2024-08-23 15:59:11 -07:00
Rose Thompson
167878aee4 Commet out debug code in fpga synth script. 2024-08-23 14:46:01 -07:00
Rose Thompson
b471913d9f On the way to making vcu108 work again. 2024-08-23 14:45:22 -07:00
Rose Thompson
4d56b3ca96 Maybe improvements to fpga synthesis. 2024-08-23 13:00:22 -07:00
Rose Thompson
fc80bf1251 More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
Rose Thompson
8d40a0a092 Changed names of fpga IP modules to match textbook. Updated boot.h to 
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
 2024-08-22 13:56:50 -07:00
Rose Thompson
faffecf891 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 11:02:17 -07:00
Rose Thompson
01b623b8c4 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 11:02:08 -07:00
Rose Thompson
113d71f1a0 More name updates. 2024-08-21 10:51:24 -07:00
Rose Thompson
f603d21826 Updated my name in multiple locations. 2024-08-21 10:50:39 -07:00
Jacob Pease
d8b75440b6 With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests. 2024-08-20 16:24:37 -05:00
Jacob Pease
baad4e0fd2 With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests. 2024-08-20 16:24:37 -05:00
Jacob Pease
43b17b5058 Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose. 2024-08-20 14:40:50 -05:00
Jacob Pease
9ac889e3e8 Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose. 2024-08-20 14:40:50 -05:00
Jacob Pease
9fae5dfc0a Added dynamic SDC Clock selector in bootloader code. 2024-08-20 12:19:49 -05:00
Jacob Pease
4a1abb1d17 Added dynamic SDC Clock selector in bootloader code. 2024-08-20 12:19:49 -05:00
Jordan Carlin
4d68664e32 FPGA Makefile refactoring 2024-08-15 11:58:40 -07:00
Jordan Carlin
8ca4a5f20e
FPGA Makefile refactoring 2024-08-15 11:58:40 -07:00
Rose Thompson
375b0d0638 Merge pull request #902 from jordancarlin/build_zsbl 
Build zsbl in main Makefile
 2024-08-15 07:49:07 -07:00
Rose Thompson
e0784b2129
Merge pull request #902 from jordancarlin/build_zsbl 
Build zsbl in main Makefile
 2024-08-15 07:49:07 -07:00
Jordan Carlin
6d77398c95 Update linker scripts to avoid hardcoded /opt/riscv 2024-08-09 20:15:28 -07:00
Jordan Carlin
564ce83e11
Update linker scripts to avoid hardcoded /opt/riscv 2024-08-09 20:15:28 -07:00
Jordan Carlin
08506b5872 Remove boot.mem 2024-08-08 20:27:51 -07:00
Jordan Carlin
16e2d65865
Remove boot.mem 2024-08-08 20:27:51 -07:00
David Harris
77c2a86cef Merge pull request #869 from jordancarlin/installation 
Installation and setup overhaul
 2024-08-08 15:39:23 -07:00
David Harris
bc70f0b933
Merge pull request #869 from jordancarlin/installation 
Installation and setup overhaul
 2024-08-08 15:39:23 -07:00
Jacob Pease
6e8c210e09 Commented out rvvi debug probes in wally.tcl. 2024-08-08 13:52:53 -05:00
Jacob Pease
8c96c06022 Commented out rvvi debug probes in wally.tcl. 2024-08-08 13:52:53 -05:00
Jacob Pease
660da55451 Turned off RVVI by default. 2024-08-08 13:50:11 -05:00
Jacob Pease
ed0c826d74 Turned off RVVI by default. 2024-08-08 13:50:11 -05:00
Jordan Carlin
357175f1c8 Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-08-07 20:22:55 -07:00
Jordan Carlin
76eef03fe4
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-08-07 20:22:55 -07:00
Jacob Pease
f8f16d2d34 Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv 2024-08-06 17:36:42 -05:00
Jacob Pease
2dc7e0f76f Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv 2024-08-06 17:36:42 -05:00
Jacob Pease
89ecc10451 Added header to new bootloader files. 2024-08-06 17:28:50 -05:00