Jacob Pease
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83b0a83d5c
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Removed HSELEXTSDC and fixed SD card pin definitions.
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2024-08-02 15:35:18 -05:00 |
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Jacob Pease
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11a057b0b3
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Updated wally source files for zsbl testing.
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2024-08-02 15:33:57 -05:00 |
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Jacob Pease
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897f6561cd
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New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently.
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2024-08-02 15:19:52 -05:00 |
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Jacob Pease
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fcd88d6e6f
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Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display.
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2024-08-02 15:14:30 -05:00 |
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Jacob Pease
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38071d8267
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Updated formatting of gpt.c and boot.c.
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2024-07-31 11:12:05 -05:00 |
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Jacob Pease
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ee980e39f3
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Added function to set SPI clock speed.
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2024-07-31 11:00:44 -05:00 |
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Jacob Pease
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c4ae17c679
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Cleaned up code formatting a bit and added ability to set the SD card clock speed.
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2024-07-31 10:59:41 -05:00 |
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Jacob Pease
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a263f836f2
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Added extra UART macros and functions for code readability and the ability to print decimal numbers.
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2024-07-31 10:58:15 -05:00 |
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Jacob Pease
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3975f60299
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Added carriage returns to line feed characters. UART messages print properly now.
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2024-07-25 13:05:57 -05:00 |
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Jacob Pease
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a36e846b02
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Changed formatting and added new UART divsor calculation from OpenSBI.
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2024-07-25 13:04:27 -05:00 |
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Jacob Pease
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336a413f31
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Added ability to split boot.memfile into boot.mem and data.mem.
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2024-07-25 11:19:15 -05:00 |
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Jacob Pease
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0dae881a0d
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Fixed SDCCLK name discrepency.
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2024-07-24 22:48:31 -05:00 |
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Jacob Pease
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ebdf25a53b
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Commented out references to old axi IP from wally.tcl.
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2024-07-24 22:47:15 -05:00 |
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Jacob Pease
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2caf9e93be
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Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram.
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2024-07-24 22:46:24 -05:00 |
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Jacob Pease
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d15be492cb
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Masked lower byte when writing to DLL.
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2024-07-24 22:44:27 -05:00 |
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Jacob Pease
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286d80de7e
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Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future
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2024-07-24 22:43:47 -05:00 |
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Jacob Pease
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0107a400d1
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Added uart header to gpt.c.
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2024-07-24 22:43:16 -05:00 |
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Jacob Pease
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f1cc7dd5a3
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Fixed verilog bugs.
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2024-07-23 17:26:39 -05:00 |
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Jacob Pease
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dcb2edf888
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Fixed syntax bugs. inline functions are now static and in the spi.h header.
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2024-07-23 17:00:32 -05:00 |
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Jacob Pease
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5f0addd69a
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Initial pass on SPI based bootloader code finished.
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2024-07-23 16:33:49 -05:00 |
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Jacob Pease
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a8b9e7776b
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Added some minor error checking to gpt.c.
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2024-07-23 16:32:52 -05:00 |
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Jacob Pease
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ab00ea5a5c
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Added sd_read64 to help with block reads and crc checking.
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2024-07-23 16:32:29 -05:00 |
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Jacob Pease
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57eeba5c8c
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Progress made on implementing new disk read function.
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2024-07-23 15:47:23 -05:00 |
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Jacob Pease
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9ccb0eb027
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Removed references to card_type.
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2024-07-23 15:46:18 -05:00 |
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Jacob Pease
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bf65cd2817
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Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c
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2024-07-23 14:18:42 -05:00 |
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Jacob Pease
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b05052311f
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Added sd_cmd and utility SPI functions.
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2024-07-22 16:57:04 -05:00 |
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Jacob Pease
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cec39fd3aa
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Added new SDC clock constraint.
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2024-07-22 13:05:16 -05:00 |
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Jacob Pease
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a506d76149
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Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
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2024-07-22 12:36:39 -05:00 |
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Jacob Pease
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e91d2c8b14
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Corrected the CRC7 code with the right sequence of instructions.
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2024-07-22 01:19:10 -05:00 |
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Jacob Pease
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c7d869bc96
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Added inital spi based sd card code. Working on CRC7 code that works.
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2024-07-20 14:00:43 -05:00 |
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Jacob Pease
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53b2a51c89
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Added tentative spi_send_byte function.
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2024-07-19 12:30:32 -05:00 |
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Jacob Pease
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34e89e842c
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Added initial spi code to fpga/zsbl
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2024-07-19 11:35:12 -05:00 |
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Ross Thompson
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ab1ee3d69b
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Removed *** from IFU, lrcs.
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2024-06-19 09:40:35 -07:00 |
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Ross Thompson
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c5dac4d775
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Removed *** from fpga top.
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2024-06-19 09:28:21 -07:00 |
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Jacob Pease
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7a417d7a6c
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Added true bootloader to fpga/zsbl directory.
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2024-05-31 15:28:25 -05:00 |
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Jacob Pease
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3f7659c8ad
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Removed old fpgaTop.v file.
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2024-05-30 16:15:19 -05:00 |
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Jacob Pease
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7ecd1c7d5f
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The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
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2024-05-30 15:48:27 -05:00 |
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Rose Thompson
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8123695831
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Maded insert_debug_comment.sh compatible with cygwin.
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2024-04-22 10:48:34 -05:00 |
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Rose Thompson
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3bed733301
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Fixed fpga to work with the updated regression changes.
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2024-04-22 10:42:01 -05:00 |
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Rose Thompson
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c1221e6608
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Fixed insert_debug_comment.sh to work with the older version of bash.
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2024-04-16 10:55:26 -05:00 |
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Rose Thompson
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6097444b5a
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Added missing file for compiling the fpga zero stage bootloader.
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2024-04-11 10:30:56 -05:00 |
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Rose Thompson
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60f96112db
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Moved the zero stage boot loader to the fpga directory.
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2024-03-01 10:23:55 -06:00 |
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Rose Thompson
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cc7f433ce0
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Update the fpga scripts to use the new derivative configs.
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2024-01-31 13:19:28 -06:00 |
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David Harris
|
45e2317636
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Added Wally github address to header comments
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2024-01-29 05:38:11 -08:00 |
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Rose Thompson
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7693c5d4e2
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Updates to fpga top level.
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2023-12-15 15:32:05 -06:00 |
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Rose Thompson
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26cd22c388
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Replaced fpga's verilog top with system verilog.
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2023-12-15 13:42:52 -06:00 |
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Rose Thompson
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dab9d7ab3c
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Replaced fpga top level verilog with system verilog.
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2023-12-15 13:07:08 -06:00 |
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Rose Thompson
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34631c54d3
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Get's the fpga building again after the git history rewrite.
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2023-12-14 17:08:25 -06:00 |
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Jacob Pease
|
7e494f2d3b
|
Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.
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2023-12-01 18:59:18 -06:00 |
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Jacob Pease
|
71066cae12
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Modified FPGA Makefile to override with relative path. FPGA boots now.
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2023-11-30 17:51:15 -06:00 |
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