79 Commits

Author	SHA1	Message	Date
naichewa	7dd3f24d6c	Merge branch 'main' into spi	2023-10-30 17:01:41 -07:00
David Harris	f6a7f707bd	Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.	2023-10-30 09:56:17 -07:00
naichewa	0ff9ce527d	Merge branch 'main' into spi	2023-10-16 22:59:50 -07:00
David Harris	ac4216b43d	Incorporated new AMO tests from riscv-arch-test	2023-10-16 10:25:45 -07:00
David Harris	6245748ed7	Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.	2023-10-15 15:31:03 -07:00
David Harris	b4891d88db	Added WALLY minfo test for rv32	2023-10-15 06:48:22 -07:00
naichewa	aa5abfc8e8	always working after reg bit swizzle changes	2023-10-13 14:22:32 -07:00
naichewa	d5d4f9d044	transferred spi changes in ECA-authorized commit	2023-10-12 13:36:57 -07:00
David Harris	d526d28804	Added MENVCFG.HADE bit and updated SVADU to depend on this bit	2023-10-04 09:34:28 -07:00
David Harris	8d3ff59673	Completed basic tests of svnapot and svpbmt	2023-08-28 06:57:35 -07:00
Ross Thompson	cd3349bd26	Added rv32 cboz test.	2023-08-24 17:02:53 -05:00
Ross Thompson	7d51690b7c	Oups forgot to include the 32-bit cbom test in previous commit.	2023-08-24 09:04:41 -05:00
David Harris	c137a1c8cf	Fixed timer interrupt testing	2023-06-09 17:20:41 -07:00
David Harris	b70b0c7c5e	Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare	2023-06-09 14:40:01 -07:00
Kip Macsai-Goren	34200e8c76	restored original virt mem tests when svadu is not supported	2023-04-11 18:47:08 -07:00
Kip Macsai-Goren	c4766c8a02	renamed virt mem tests to include svadu	2023-04-11 18:46:37 -07:00
Kip Macsai-Goren	b2d6084eea	removed unnecessary 'deadbeef's at the end of reference outputs	2023-04-11 18:32:04 -07:00
Kip Macsai-Goren	a82c0a7780	Modified virt mem tests to do correct r/w when svadu is enabled	2023-04-11 18:08:30 -07:00
Kip Macsai-Goren	e0b938b409	Removed Trap outputs from writes covered by SVADU	2023-04-11 17:41:57 -07:00
Kip Macsai-Goren	a7c9d3d37b	ported medelg fixes to 32 bit tests. Requires a make allclean	2023-03-29 16:31:28 -07:00
David Harris	2e5c50e24a	Fixed RV32 tests after PMP fix	2023-03-28 08:35:23 -07:00
Kip Macsai-Goren	758da62a9f	ported fixes to 32 bit tests	2023-03-24 11:22:39 -07:00
Kip Macsai-Goren	964084f0b3	added fs=00 to status fp enabled test	2022-12-22 15:15:53 -08:00
Kip Macsai-Goren	d25d699800	Added status.tvm bit test that passes make and regression	2022-12-22 14:43:22 -08:00
Kip Macsai-Goren	4c81b6fa5f	added corrrect scr read out of uart to periph test	2022-12-05 20:16:02 -08:00
Kip Macsai-Goren	51e78d9e48	added copies of 64 bit tests to 32 bit periph and priv tests	2022-12-05 20:16:02 -08:00
Kip Macsai-Goren	540d6c2f41	added -01 to all WALLY tests	2022-12-05 20:16:02 -08:00
Kip Macsai-Goren	6e45698b86	Added test for UART FIFO timeout. Does not pass regression	2022-10-25 05:35:56 +00:00
Kip Macsai-Goren	e603973dff	added xlen and endianness test edits. xlen passes but endinanness still won't make	2022-09-26 05:03:19 +00:00
Kip Macsai-Goren	0cc7f5719c	ported endianness tests to 32 bits (not tested in regression yet)	2022-09-18 00:10:29 +00:00
David Harris	898dbc8e74	Completed PLIC-S tests. Regression working. This completes peripheral tests.	2022-08-03 09:33:56 -07:00
David Harris	cab0349701	Started plic-s tests	2022-08-03 03:48:08 +00:00
David Harris	93d7d7179e	Added parity and stop bit tests to UART	2022-07-28 04:35:51 +00:00
David Harris	429bdae1c4	Fixed UART reference output	2022-07-27 22:16:38 +00:00
David Harris	b08c87cb47	Finished UART test	2022-07-27 04:06:59 +00:00
slmnemo	7348af7fd5	Updated reference file for UART test	2022-07-26 09:39:31 -07:00
slmnemo	bfced6bfe8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-22 17:13:38 -07:00
slmnemo	ca4511b6dc	Fixed UART FIFO bugs and added FIFO tests	2022-07-22 17:13:19 -07:00
Daniel Torres	4da96c5791	fixed 32priv tests, now passing	2022-07-22 15:35:20 -07:00
Daniel Torres	24828db612	changes to test.vh for compatability	2022-07-22 15:00:48 -07:00
slmnemo	141f2a40e4	UART updates and PMA fix	2022-07-22 14:49:03 -07:00
slmnemo	9cca567136	Added test comments to reference output	2022-07-22 12:35:59 -07:00
Daniel Torres	0e75142ef4	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-22 11:16:09 -07:00
Daniel Torres	95fdd408ee	commiting current changes to riscof wally tests	2022-07-22 11:14:04 -07:00
slmnemo	d38369e8bf	Added new PLIC and UART tests	2022-07-22 07:12:55 -07:00
slmnemo	6b2125ab0e	Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests.	2022-07-05 18:21:17 -07:00
slmnemo	228028c837	Add CLINT tests from book	2022-06-27 20:09:58 -07:00
slmnemo	033ec135f8	Added reset read testcodes to GPIO	2022-06-27 18:56:35 -07:00
slmnemo	cb8ae72326	Fixed error in GPIO signature	2022-06-23 14:12:28 -07:00
David Harris	db459c3380	GPIO tests	2022-06-23 21:06:11 +00:00