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584 Commits

Author SHA1 Message Date
Alec Vercruysse
214abc7006 Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE 
Some address options are only used in the D$ case.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
6dce58125b Remove FlushStage Logic from CacheLRU 
For coverage.

LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.

Update cache.sv to reflect cacheLRU edit.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
3fc6bb0c40 Exclude (FlushStage & SetValidWay) condition for RO caches 
Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.

I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
 2023-04-12 01:15:35 -07:00
Limnanthes Serafini
fdb81e44c9 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Alexa Wright
34fd402f23 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
Ross Thompson
132016f131 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-09 12:19:44 -05:00
Kevin Thomas
640310cf94 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
David Harris
4a2f641348 Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00
David Harris
495f2ed274 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
David Harris
5119222c2f Commented WFI non-flush in writeback stage of hazard unit 2023-04-07 21:27:13 -07:00
David Harris
7ad8d7f774 Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
David Harris
c24e81c57f Division cleanup 2023-04-06 21:42:34 -07:00
David Harris
ce931d1fc5 Simplified integer division preprocessing in fdivsqrt 2023-04-06 16:43:28 -07:00
David Harris
1569bfbb98 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Ross Thompson
fe922c8fac Fixed syntax error. 2023-04-06 15:10:55 -05:00
Ross Thompson
270b3371f1 Added note about strange vivado behavior not inferring block ram. 2023-04-06 15:09:35 -05:00
Ross Thompson
d121364997 Similifed the no byte write enabled version of the sram model. 2023-04-06 14:18:41 -05:00
Kevin Thomas
1931859c45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-06 12:38:41 -05:00
David Harris
52dcd63d1e
Merge pull request #211 from ross144/main 
Fixes the issue introduced by the fix for issue 203
 2023-04-05 21:50:32 -07:00
Ross Thompson
1478115faf Fixed wally64/32priv test hangup. 
The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
 2023-04-05 23:13:45 -05:00
Kevin Thomas
e70a081924 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 17:43:43 -05:00
Ross Thompson
f2c26ff886
Merge pull request #206 from AlecVercruysse/coverage2 
i$ coverage improvements
 2023-04-05 17:29:35 -05:00
Alec Vercruysse
2a3d9f8c89 Update ram1p1rwe (ce & we) coverage exlusion explanation 2023-04-05 14:54:58 -07:00
Kevin Thomas
c4a9bb4269 Formating white space 2023-04-05 15:30:55 -05:00
Kevin Thomas
7345927cb1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 15:04:12 -05:00
Ross Thompson
d1ac175e27 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 14:55:12 -05:00
Alec Vercruysse
61e19c2ddf Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE 
To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
d3a988c96c make Cache Flush Logic dependent on !READ_ONLY_CACHE 
read-only caches do not have flush logic since they do not have to
deal with dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
247af17b6b remove ClearValid from cache 
The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
3867142f10 change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe 
the byte write-enables were always tied high, so we can use
RAM without byte-enable to increase coverage.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
4993b1b426 turn off ce coverage for ram1p1rwe 
According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.

For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.

Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
277f507e9a add ram1p1rwe for read-only cache ways (remove byte-enable) 
- increases coverage
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
c0206cfcb3 fix typo in cachway setValid input comment 2023-04-05 11:48:18 -07:00
Alec Vercruysse
270200bc1c put cacheLRU coverage explanation on another line 
the `: explanation` syntax was not working
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
c41f4d2e7b Exclude CacheLRU log2 function from coverage 2023-04-05 11:48:18 -07:00
Ross Thompson
7c2512446c Progress on bug 203. 2023-04-05 13:20:04 -05:00
Kevin Thomas
5e5842893b Minor change with the IFU in the decompress module, in the compressed instruction truth table. 
The truth table is already fully covered, removed redundant last case checking
 2023-04-05 10:27:52 -05:00
David Harris
b7b1f2443f Fixed WFI to commit when an interrupt occurs 2023-04-04 09:32:26 -07:00
Ross Thompson
c21a5aaaf7
Merge pull request #194 from davidharrishmc/dev 
Bit manipulation support in ImperasDV.  Test improvements.
 2023-04-04 09:13:27 -05:00
Kevin Kim
d7deed1690
Merge branch 'openhwgroup:main' into zbc_optimize 2023-04-03 23:45:49 -07:00
Kevin Kim
ce8a401a84 reduced mux3 to mux2 for input signal to clmul 2023-04-03 22:53:46 -07:00
David Harris
57ee9f3a5a Merged priv.S edits 2023-04-03 18:07:14 -07:00
Sydeny
8cfd221444 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-03 13:41:55 -07:00
Ross Thompson
91803dc684
Merge pull request #178 from AlecVercruysse/coverage 
Improve I$ coverage by simplifying logic
 2023-04-03 14:22:46 -05:00
David Harris
af8f1ab786 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-03 06:13:16 -07:00
Sydeny
7e5e9d928e Manual merge for fctrl.sv, fpu.S, and ifu.S files 2023-04-03 01:55:23 -07:00
Sydeny
58eed1bba2 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-03 01:54:27 -07:00
Sydney Riley
440e41bb3e expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions. 2023-04-02 23:51:34 -07:00
Kevin Kim
03bf8f373f Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup 2023-04-02 21:14:35 -07:00
Kevin Kim
5e7bbeddd1 removed comparator flag to ALU 2023-04-02 21:14:31 -07:00
Kevin Kim
f35b287e66 signal renaming on bitmanip alu and alu 2023-04-02 18:42:41 -07:00
Kevin Kim
9a4fa6ce96 changed signal names on clmul and zbc to match book 2023-04-02 18:28:09 -07:00
David Harris
03b4f6660c Coverage improvement: ieu, hazard, priv 2023-03-31 08:34:34 -07:00
David Harris
b95730e3a1 Coverage improvements in ieu, hazard units 2023-03-31 08:33:46 -07:00
Marcus Mellor
984d4b9918 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-31 10:29:10 -05:00
Mike Thompson
a28a457099
Merge pull request #179 from davidharrishmc/dev 
Fixed broken regression: privileged tests and build root
 2023-03-31 10:56:27 -04:00
Marcus Mellor
c7ec42eaab Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-31 09:54:02 -05:00
Marcus Mellor
913cdecb65 Address comments in openhwgroup/cvw#180 2023-03-31 09:51:33 -05:00
Kevin Kim
97181e063b only pass in relevant comparator flag to ALU 2023-03-30 19:15:33 -07:00
Kevin Kim
bd1ac13f5f Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup 2023-03-30 19:04:41 -07:00
Kevin Kim
b43e4d8d0d
Merge branch 'openhwgroup:main' into bitmanip_cleanup 2023-03-30 19:04:36 -07:00
Marcus Mellor
64f15d48de Disable coverage for branches tested in fpu.s 2023-03-30 19:44:55 -05:00
David Harris
77d5f1c81b Refactored InstrValidNotFlushed into CSR Write signals 2023-03-30 17:06:09 -07:00
David Harris
25cd1cc432 Started factoring out InstrValidNotFlushed from CSRs 2023-03-30 14:56:19 -07:00
David Harris
a4ae1b9cbb fctrl updated and buildroot working again 2023-03-30 13:17:15 -07:00
David Harris
fc01f45c80 fctrl continued cleanup 2023-03-30 13:07:39 -07:00
David Harris
e68e473da9 fctrl continued cleanup 2023-03-30 13:05:56 -07:00
David Harris
b07c71ea41 Started to clean up fctrl 2023-03-30 12:57:14 -07:00
Alec Vercruysse
132074523f Make entire cache write path conditional on READ_ONLY_CACHE 2023-03-30 10:32:40 -07:00
Kip Macsai-Goren
94f03b0d78 unnecessary comments cleanup 2023-03-29 19:32:57 -07:00
Kip Macsai-Goren
da905b4eb9 Resolved ImperasDV receiving incorrect cause values 2023-03-29 15:04:56 -07:00
Alec Vercruysse
dac011c1d2 icache coverage improvements by simplifying logic 2023-03-29 13:04:00 -07:00
David Harris
de2a0da9e9 Reduced number of bits in mcause and medeleg registers 2023-03-29 07:02:09 -07:00
David Harris
96e3c3bea8 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-29 06:19:10 -07:00
David Harris
043e4fe5f4 Simplified fctrl 2023-03-28 21:13:48 -07:00
Alec Vercruysse
bfb4f0d6eb add check for legal funct3 for IW instructions 2023-03-28 15:59:48 -07:00
David Harris
77affa7ccd Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-28 14:33:18 -07:00
Ross Thompson
73e6972f0b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-28 16:31:50 -05:00
David Harris
5e352bf72e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-28 14:27:08 -07:00
Ross Thompson
69f6b291c6 Possible fix for issue 148. 
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.

I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.

This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
 2023-03-28 14:47:08 -05:00
Kevin Kim
adabb7c236 comment formatting 2023-03-28 11:40:19 -07:00
Kevin Kim
4c9670a082
Merge branch 'openhwgroup:main' into bitmanip_cleanup 2023-03-28 11:31:18 -07:00
David Harris
f0cab709f2 Added support (untested) for half and quad conversions 2023-03-28 10:53:06 -07:00
David Harris
40311c4f62 fixed fp->fp conversions 2023-03-28 10:35:41 -07:00
David Harris
e5955c5dd8 support more fp -> fp conversions 2023-03-28 10:28:01 -07:00
David Harris
fd2d08f501 Fixed fmv decoder 2023-03-28 10:21:33 -07:00
Ross Thompson
d55b0c8c1f
Merge pull request #169 from davidharrishmc/dev 
PMP Fix to issue 132
 2023-03-28 11:49:00 -05:00
David Harris
aa31b45d88 Fixed RV32 tests after PMP fix 2023-03-28 08:35:23 -07:00
David Harris
39d3bf8e8a Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests 2023-03-28 06:58:17 -07:00
David Harris
20ebf7e536 CSRS privileged coverage test 2023-03-28 04:37:56 -07:00
Ross Thompson
8504774a11 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-27 11:55:19 -05:00
David Harris
edaa306240 Removed unnecessary monitor 2023-03-27 09:52:38 -07:00
Ross Thompson
88c572d9bb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-27 10:22:48 -05:00
Lee Moore
39ac6be103
Merge branch 'openhwgroup:main' into add-linux 2023-03-27 09:44:13 +01:00
Kevin Kim
f3edbcea15 removed unnecessary signal indices 2023-03-26 20:06:55 -07:00
Kevin Kim
b4d6021b3b removed unneccesary input signal from zbb 2023-03-26 19:39:49 -07:00
Ross Thompson
3fc0c4b34e Modified plic and uart to remove async reset. This removes vivado critical warning. 2023-03-24 20:37:48 -05:00
Ross Thompson
78ab9f59af Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
Ross Thompson
1f37e6dcea Renamed controllerinputstage to controllerinput to match book. 2023-03-24 17:57:02 -05:00
David Harris
0dc6f9b991 Merged ross's spacing fixes 2023-03-24 15:47:26 -07:00
David Harris
46e0841011
Merge pull request #159 from ross144/main 
Renamed signal to match book
 2023-03-24 15:34:59 -07:00
Ross Thompson
730f3ac84e Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
Ross Thompson
0511c73e22 Replaced tabs -> spaces cache. 2023-03-24 15:15:38 -05:00
Ross Thompson
1ff15c3882 Updated EBU to replace tabs with spaces. 2023-03-24 15:01:38 -05:00
Kevin Kim
eb8fe3ed17 Zero/Sign extend mux in Shifter, Zero extend mux in Bitmanip alu 2023-03-24 11:52:51 -07:00
David Harris
a5e569245b Shifter capitalization 2023-03-24 09:01:07 -07:00
Ross Thompson
2956c11dbc Renamed ebu signal. 2023-03-24 10:51:04 -05:00
David Harris
9f1c1958a6 Query about CondExtA 2023-03-24 08:35:33 -07:00
David Harris
34e0b3bc61 Shifter sign simplification and capitalization 2023-03-24 08:27:30 -07:00
David Harris
25a1ea7d23 FPU detect illegal instructions 2023-03-24 08:12:32 -07:00
David Harris
59f948d47c Start of EBU coverage tests 2023-03-24 08:12:02 -07:00
David Harris
d04f4cedf6 ALUControl Elimination 2023-03-24 08:10:48 -07:00
David Harris
ac0b669518 Merged ALUOp into ALUControl to simplify ALU mux 2023-03-24 07:28:42 -07:00
David Harris
9ffac8315b Simplified rotate source to shifter 2023-03-24 06:49:26 -07:00
David Harris
c6561fffd4 BMU simplifications 2023-03-24 06:18:06 -07:00
David Harris
e67b077a3e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-24 05:59:48 -07:00
Kevin Kim
3ec4b23ff5 minor formatting 2023-03-23 22:28:21 -07:00
Kevin Kim
f07397df76 comments 2023-03-23 22:22:25 -07:00
Kevin Kim
125cb0ce44 removed redundant signals 
-fixed some comments too
 2023-03-23 22:20:37 -07:00
Kevin Kim
969b2723ef bitmanip alu submodule passes lint and regression 2023-03-23 21:56:03 -07:00
Kevin Kim
e2a5c87b73 more progress. Failing regression 2023-03-23 20:42:49 -07:00
Kevin Kim
1eb04d9747
Merge branch 'openhwgroup:main' into bitmanip-alu 2023-03-23 19:53:50 -07:00
David Harris
dc156cc09c Removed unnecessary XZero from fdivsqrt 2023-03-23 17:25:59 -07:00
David Harris
7e947023c1 Merged BMU 2023-03-23 17:24:40 -07:00
Kevin Kim
f9fc30e1cb fixed rori rv32 bug 2023-03-23 16:06:46 -07:00
Kevin Kim
7b1567829c more progress on bitmanip alu modularization 2023-03-23 16:02:38 -07:00
David Harris
f8ad1b3db8 Improved IEU and bitmanip test coverage 2023-03-23 14:24:41 -07:00
Kevin Kim
e5be0bd2fd started bitmanip alu modularization 2023-03-23 14:02:28 -07:00
David Harris
99c471ccfe Added csrwrites.S test case for privileged tests 2023-03-23 10:55:32 -07:00
Kevin Kim
bfaf646ed2 Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip 2023-03-22 10:34:19 -07:00
Kevin Kim
cd50018087 remove outdated 2023-03-22 10:34:17 -07:00
Kevin Kim
605f41cd55
Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 10:33:15 -07:00
Kevin Kim
b3fbdba7f3 updated header comments to indicate chapter 15 2023-03-22 10:31:21 -07:00
Kevin Kim
c197a040c8 remove helper python script 2023-03-22 10:27:59 -07:00
Kevin Kim
b9b8023674 formatting 2023-03-22 10:26:04 -07:00
Kevin Kim
bc2bbc0529 min/max mux optimize 2023-03-22 10:25:54 -07:00
Kevin Kim
80a490888a formatting 2023-03-22 10:14:12 -07:00
eroom1966
1c3c8be148 support linux 2023-03-22 17:10:32 +00:00
David Harris
c4c7f5378e Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault 2023-03-22 06:29:30 -07:00
David Harris
32c54db595 Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0 2023-03-22 04:41:57 -07:00
David Harris
77fb1b57f4 Fix Issue 145 2023-03-22 04:33:14 -07:00
Kevin Kim
2e149f9a31 Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-21 11:20:05 -07:00
David Harris
376bbcc71d Renamed intdivrestoring to div 2023-03-21 05:51:02 -07:00
David Harris
0fd385e5de Renamed intdivrestoring to div 2023-03-20 16:22:06 -07:00
Kevin Kim
73fbc21aab formatting 2023-03-20 14:25:05 -07:00
Kevin Kim
37b73ea42e more structural mux changes 2023-03-20 14:23:54 -07:00
Kevin Kim
7a6d1ab393 added bitmanip 64 tests to updated regression script 
+ alu structural mux changes
 2023-03-20 14:19:39 -07:00
Kevin Kim
728be29ce3 formatting 2023-03-20 13:09:49 -07:00
Kevin Kim
07a43e1935 Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-20 13:06:10 -07:00
David Harris
0ecde4ab4f formatting cleanup 2023-03-20 12:45:10 -07:00