more structural mux changes

This commit is contained in:
Kevin Kim 2023-03-20 14:23:54 -07:00
parent 7a6d1ab393
commit 37b73ea42e

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@ -42,6 +42,6 @@ module byteUnit #(parameter WIDTH=32) (
assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
end
assign ByteResult = (ByteSelect) ? OrcBResult : Rev8Result;
mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult);
endmodule