Ross Thompson
2598f08782
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Katherine Parry
6216bd7172
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
Ross Thompson
ae6140bd94
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
bbracker
a7f810e2c4
trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug
2021-06-26 08:30:58 -04:00
bbracker
61495f74ac
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-26 08:29:37 -04:00
bbracker
aa8da43743
temporarily disable PMP checking for EBU accesses.
2021-06-26 07:19:51 -04:00
bbracker
59b2a49854
split intermediate GDB output file into smaller files for better debug experience
2021-06-26 07:18:26 -04:00
Ross Thompson
8dfbf60b67
AMO and LR/SC instructions now working correctly.
...
Page table walking is not working.
2021-06-25 15:42:07 -05:00
Abe
b6426c5fbf
Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs
2021-06-25 16:42:03 -04:00
Abe
ff8b421e6c
Fixed Coremark Score output printing. Also made it so that the loop that sets the iteration count increments iterations by 1 instead by increasing it by a factor of 10 each time (which was overkill for the timing that's needed to exit the loop)
2021-06-25 16:27:23 -04:00
Ross Thompson
a4266c0136
Some progress. Had to change how the page table walker got it's ready.
2021-06-25 15:07:41 -05:00
Ross Thompson
9fd1761fd6
Working through a combo loop.
2021-06-25 14:49:27 -05:00
Ross Thompson
17636b3293
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
bbracker
9927f771cc
linux testbench now ignores HWRITE glitches caused by flush glitches
2021-06-25 09:28:52 -04:00
bbracker
2694a7a43f
made testbench-linux's PCDwrong be FlushD
2021-06-25 08:15:19 -04:00
bbracker
4e09793a9a
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
bbracker
aac9b46a1f
changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
1485d29dde
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
389b9a510e
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Katherine Parry
bc8d660bc5
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
ced5039776
Revert "fixed forwarding"
...
This reverts commit 0f4a4a6ade
2021-06-24 17:39:37 -04:00
Ross Thompson
d8183e59e4
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
732551d6be
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Ross Thompson
0377d3b2c9
Progress.
2021-06-24 13:05:22 -05:00
bbracker
0f4a4a6ade
fixed forwarding
2021-06-24 11:20:21 -04:00
bbracker
3ae4cd951a
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
3d6b422e34
regression can overcome the fact that buildroots UART prints stuff
2021-06-24 02:00:01 -04:00
bbracker
409a73604c
whoops meant to remove notifications from busybear, not buildroot
2021-06-24 01:54:46 -04:00
bbracker
55cf205222
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-24 01:42:41 -04:00
bbracker
b84419ff4e
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
547bf1d0af
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
abe5bc90bf
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
6134c22aca
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Katherine Parry
44af47608c
fpu clean-up
2021-06-23 16:42:40 -04:00
Ross Thompson
d5063bee7d
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
5de7a46237
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-23 09:34:42 -05:00
David Harris
718630c378
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
4189b2d4a7
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
1972d83002
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6dc54acde8
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
ae0fa90450
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
b43a8885cd
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
Ross Thompson
e7d8d0b337
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-22 15:47:16 -05:00
Katherine Parry
9eb6eb40bf
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
d6c5c61b59
Fixed mask assignment error, made usage, variables more clear
2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
b78c09baed
Continued fixing fsm to work right with svmode
2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
852bb9296f
updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
2021-06-22 11:21:11 -04:00
bbracker
56b0d4d016
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
Ross Thompson
03084a4128
Icache now uses physical lenght bits rather than XLEN.
2021-06-21 16:41:09 -05:00
Ross Thompson
8ec5b0c4f1
Improved some names in icache.
2021-06-21 16:40:37 -05:00
