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639 Commits

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Author SHA1 Message Date
Noah Boorstin
7fb2ebec50 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Jarred Allen
789c189260 Another tweak to regression-wally.py comments 2021-03-23 00:18:38 -04:00
Jarred Allen
34cc9b4aeb Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
e4ebb4e31e Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
2c4eda2ba3 Slight change to regression-wally.py comments 2021-03-23 00:02:40 -04:00
Jarred Allen
c47a80213e Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Noah Boorstin
3c131bb2bd start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
1592332d41 Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
43d23e3d9b busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
4160bf50b0 busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
4be19421c4 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
b4166e9fd0 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
bbracker
c3a6d6bf42 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
Jarred Allen
307e33bc7e Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00
Jarred Allen
99fa8beef3 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
7350b9f18f busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
507d8ed120 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
c4fb51fad1 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
2269879459 Merge branch 'main' into cache 2021-03-22 13:47:48 -04:00
bbracker
eea7e2e47e first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Katherine Parry
9af0ad815c fixed various bugs in the FMA 2021-03-21 22:53:04 +00:00
Jarred Allen
bab0e3b90f Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
e32291bcc2 Put Imperas testbench back 2021-03-20 18:19:51 -04:00
Jarred Allen
066dc2caac Fix bug with PC incrementing 2021-03-20 18:06:03 -04:00
Jarred Allen
e531a1b5ee Merge branch 'main' into cache 2021-03-20 17:56:25 -04:00
Jarred Allen
665c244ba1 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
43a8cb0354 Revert "Change flop to listen to StallF" 
This reverts commit f069b759be.
 2021-03-20 17:34:19 -04:00
Jarred Allen
639a718312 Fix conflicts in ahb-waves that snuck through manual merging 2021-03-20 17:16:50 -04:00
Jarred Allen
f069b759be Change flop to listen to StallF 2021-03-20 17:04:13 -04:00
Katherine Parry
fd381e60d7 messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic 2021-03-20 02:05:16 +00:00
Jarred Allen
50c961bbe4 Merge changes from main 2021-03-18 18:58:10 -04:00
Jarred Allen
bf2fbf49ee Add icache's read request to ahb wavs 2021-03-18 18:52:03 -04:00
bbracker
df51d9908d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
bbracker
11ba96f2e3 maybe AHB works now 2021-03-18 17:47:00 -04:00
Shreya Sanghai
804407eab7 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
181a28e875 Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
f35d3b39c8 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
859d242d81 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-18 14:36:42 -04:00
Thomas Fleming
062c4d40da Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Thomas Fleming
f04e554e35 Improve page table creation in python file 2021-03-18 14:27:09 -04:00
Noah Boorstin
847bf0b9a6 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
fa1407f6e3 everyone gets a bootram 2021-03-18 12:35:37 -04:00
Noah Boorstin
a226e24ed3 busybear: update memory map, add GPIO 2021-03-18 12:17:35 -04:00
Teo Ene
0ff785549e Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
db164462ed adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Jarred Allen
e39ead0460 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
29634f1475 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
e6661ea26a fix to last commit 2021-03-17 15:07:02 -05:00