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Configurable RISC-V Processor
434 Commits 4 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
c47a80213e
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Jarred Allen c47a80213e Small commit to see if new hook tests non-main branch
2021-03-22 23:57:01 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
.gitignore Added debug option to disable the function radix if not needed. 2021-03-10 15:17:02 -06:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md

README.md

riscv-wally

Configurable RISC-V Processor