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Author SHA1 Message Date
Ross Thompson
69a6a4800e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-11 15:42:10 -06:00
Ross Thompson
d68446cf92 Added new asserts to testbench. 2022-03-11 15:41:53 -06:00
Ross Thompson
e802deb4d6 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Kip Macsai-Goren
6ac9a626e2 added preliminary files for trap/priv tests. These DO NOT pass make yet because if interrrupt handling problems 2022-03-11 20:00:54 +00:00
Kip Macsai-Goren
c9110ebb40 removed compressed instructions from gcc make for privilege tests 2022-03-11 19:09:40 +00:00
Kip Macsai-Goren
cc07a3f31f Added interrupt support (not exiting correctly yet), macros for causing traps. 2022-03-11 19:09:16 +00:00
Ross Thompson
81a2fbb6d2 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
11e5aad38a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
04dd2f0eb5 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
a598760445 Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
bdfca503fa Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
5c16b65a16 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00
Ross Thompson
543e10ab32 Moved subwordwrite to lsu directory. 2022-03-10 18:15:25 -06:00
Ross Thompson
54abd944e2 Simplified byte write enable logic. 2022-03-10 18:13:35 -06:00
Ross Thompson
50789f9ddd Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
f7df3a0666 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
83133f8c47 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
David Harris
b1340653cf bit write update 2022-03-09 19:09:20 +00:00
David Harris
004853c312 Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
David Harris
ba9320d822 Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
Ross Thompson
2a8a1cd191 Minor cleanup to interlockfsm. 2022-03-08 23:38:58 -06:00
Ross Thompson
ac9528b450 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-08 18:05:35 -06:00
Ross Thompson
ed32801cc1 Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
534fd70f76 Marked signals for name changes. 2022-03-08 17:41:02 -06:00
David Harris
5d0b9bab6e Added more test cases and rounding modes to fma test generator 2022-03-08 23:29:29 +00:00
David Harris
582b943380 fixed setup.sh merge conflict 2022-03-08 23:21:06 +00:00
David Harris
cfa82efccc fma16_testgen.c test cases 2022-03-08 23:18:18 +00:00
Ross Thompson
acd60218b8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
cc21414051 Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
Ross Thompson
60e6c1ffa7 Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
bbracker
e3303331ef change genTrace to dump UART output to file so we can see how far parsing got 2022-03-08 09:52:17 -08:00
bbracker
51e68819c4 fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
9dbcdca433 change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers 2022-03-07 22:12:08 -08:00
bbracker
c2ac18b5de change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
bbracker
52bfd65fd3 change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state 2022-03-07 17:59:49 -08:00
bbracker
a93f36824d modify debug.sh to not rely on external GDB script 2022-03-07 11:56:04 -08:00
bbracker
74ff583f9b add debug.sh 2022-03-07 19:52:19 +00:00
Shreya Sanghai
b73f81548f removed reminant changes 2022-03-07 17:36:05 +00:00
Shreya Sanghai
b6b4d0f982 undid changes to synth script 2022-03-07 17:32:08 +00:00
Shreya Sanghai
31f17d2bf3 modified synth script to take config from outputdir 2022-03-07 17:12:43 +00:00
Shreya Sanghai
4d8e0ecf29 updated makefile to speed up synth 2022-03-07 00:09:18 +00:00
Shreya Sanghai
e4145d32ab modified makefile 2022-03-07 00:09:18 +00:00
bbracker
01eeab2131 update checkpointSweep in accordance to having removed trace parsing feature 2022-03-06 14:55:51 -08:00
bbracker
c432e2175e remove vestigial silencePipe mechanism 2022-03-06 14:54:35 -08:00
bbracker
ca6bb7c2d2 needed to initialize checkpoint directory 2022-03-06 14:51:25 -08:00