Commit Graph

556 Commits

Author SHA1 Message Date
Limnanthes Serafini
b3976daccd More cleanup 2023-04-13 21:34:50 -07:00
Limnanthes Serafini
b80a540c73 More cleanup 2023-04-13 21:02:30 -07:00
Limnanthes Serafini
53847269da More changes 2023-04-13 21:02:15 -07:00
Limnanthes Serafini
0b6ce1b031 Some cleanup 2023-04-13 21:01:57 -07:00
David Harris
48de682ea8 Merged coverage-exclusions 2023-04-13 18:15:23 -07:00
David Harris
5066cd99ab Merge pull request #237 from SydRiley/main
fctrl coverage at 100% after removing redundancies from conditionals
2023-04-13 17:10:46 -07:00
Limnanthes Serafini
95586abe09 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
034c289a36 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
David Harris
11434f05e2 Starting fdivsqrt cleanup 2023-04-13 16:53:33 -07:00
Sydeny
2b8891cefd Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Alec Vercruysse
680aee7e07 Merge branch 'main' into coverage3 2023-04-12 16:00:15 -07:00
Alec Vercruysse
01f2417524 cachefsm exclude icache logic without code reuse 2023-04-12 15:57:45 -07:00
Alec Vercruysse
cc3b2bf435 Cachefsm gate LRUWriteEn with ~FlushStage 2023-04-12 13:32:36 -07:00
Sydeny
f9566299a0 fctrl coverage at 100% after removing redundancies from conditional statements 2023-04-12 13:07:30 -07:00
Ross Thompson
10be07857c Merge pull request #229 from davidharrishmc/dev
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
2023-04-12 12:21:03 -05:00
Alec Vercruysse
1cb6e1751b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
David Harris
6b05a71152 Removed unnecessary start term from initialization muxes to simplify and improve coverage 2023-04-12 03:34:01 -07:00
David Harris
463a1e2b33 Fixed fdivsqrt to avoid going from done to busy without going through idle first 2023-04-12 02:48:40 -07:00
Limnanthes Serafini
65d29306ef Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
0ed3e80ee0 only assign ClearDirtyWay for read-write caches 2023-04-12 01:15:35 -07:00
Alec Vercruysse
4cbb9bcec6 refactor cachefsm to get full coverage
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
2023-04-12 01:15:35 -07:00
Alec Vercruysse
a1bbcd5e8a Coverage and readability improvements to LRUUpdate logic
The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
5b8c6f070e Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE
Some address options are only used in the D$ case.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
7c9f68e984 Remove FlushStage Logic from CacheLRU
For coverage.

LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.

Update cache.sv to reflect cacheLRU edit.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
68a01cb0f8 Exclude (FlushStage & SetValidWay) condition for RO caches
Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.

I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
2023-04-12 01:15:35 -07:00
Limnanthes Serafini
e5ead0f5b8 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Alexa Wright
fb517163f5 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
Ross Thompson
81074a822a Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-09 12:19:44 -05:00
Kevin Thomas
f7838b869b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
David Harris
7affe2bdca Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00
David Harris
2f4074b9c2 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
David Harris
5cdd3d57c7 Commented WFI non-flush in writeback stage of hazard unit 2023-04-07 21:27:13 -07:00
David Harris
9394389fec Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
David Harris
19c39628fa Division cleanup 2023-04-06 21:42:34 -07:00
David Harris
6db65f30b1 Simplified integer division preprocessing in fdivsqrt 2023-04-06 16:43:28 -07:00
David Harris
7ad05d9a42 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Ross Thompson
07b946bc75 Fixed syntax error. 2023-04-06 15:10:55 -05:00
Ross Thompson
4407d3310c Added note about strange vivado behavior not inferring block ram. 2023-04-06 15:09:35 -05:00
Ross Thompson
ee4cf5e94d Similifed the no byte write enabled version of the sram model. 2023-04-06 14:18:41 -05:00
Kevin Thomas
a588a9eb5d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-06 12:38:41 -05:00
David Harris
4e3af7bca7 Merge pull request #211 from ross144/main
Fixes the issue introduced by the fix for issue 203
2023-04-05 21:50:32 -07:00
Ross Thompson
e531b0103e Fixed wally64/32priv test hangup.
The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
2023-04-05 23:13:45 -05:00
Kevin Thomas
d7188d6d9c Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 17:43:43 -05:00
Ross Thompson
7cdd12a40a Merge pull request #206 from AlecVercruysse/coverage2
i$ coverage improvements
2023-04-05 17:29:35 -05:00
Alec Vercruysse
ac3569d75c Update ram1p1rwe (ce & we) coverage exlusion explanation 2023-04-05 14:54:58 -07:00
Kevin Thomas
4d30aff198 Formating white space 2023-04-05 15:30:55 -05:00
Kevin Thomas
5ac49fa31f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 15:04:12 -05:00
Ross Thompson
da9cf02ba0 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 14:55:12 -05:00
Alec Vercruysse
570e86afc3 Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE
To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
54df581ce6 make Cache Flush Logic dependent on !READ_ONLY_CACHE
read-only caches do not have flush logic since they do not have to
deal with dirty bits.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
3419ef3651 remove ClearValid from cache
The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
81125d3180 change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe
the byte write-enables were always tied high, so we can use
RAM without byte-enable to increase coverage.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
782feb6161 turn off ce coverage for ram1p1rwe
According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.

For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.

Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
8b6b96012d add ram1p1rwe for read-only cache ways (remove byte-enable)
- increases coverage
2023-04-05 11:48:18 -07:00
Alec Vercruysse
2553321158 fix typo in cachway setValid input comment 2023-04-05 11:48:18 -07:00
Alec Vercruysse
9df246e5de put cacheLRU coverage explanation on another line
the `: explanation` syntax was not working
2023-04-05 11:48:18 -07:00
Alec Vercruysse
af113c7268 Exclude CacheLRU log2 function from coverage 2023-04-05 11:48:18 -07:00
Ross Thompson
394f2d65f2 Progress on bug 203. 2023-04-05 13:20:04 -05:00
Kevin Thomas
0c80067d45 Minor change with the IFU in the decompress module, in the compressed instruction truth table.
The truth table is already fully covered, removed redundant last case checking
2023-04-05 10:27:52 -05:00
David Harris
4552f9cf8c Fixed WFI to commit when an interrupt occurs 2023-04-04 09:32:26 -07:00
Ross Thompson
52d1c19509 Merge pull request #194 from davidharrishmc/dev
Bit manipulation support in ImperasDV.  Test improvements.
2023-04-04 09:13:27 -05:00
Kevin Kim
0a1adecf8a Merge branch 'openhwgroup:main' into zbc_optimize 2023-04-03 23:45:49 -07:00
Kevin Kim
acebdeeb81 reduced mux3 to mux2 for input signal to clmul 2023-04-03 22:53:46 -07:00
David Harris
64679654ff Merged priv.S edits 2023-04-03 18:07:14 -07:00
Sydeny
a0ecd83c47 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-03 13:41:55 -07:00
Ross Thompson
91e4e64f3d Merge pull request #178 from AlecVercruysse/coverage
Improve I$ coverage by simplifying logic
2023-04-03 14:22:46 -05:00
David Harris
4e2d80476e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-03 06:13:16 -07:00
Sydeny
981e5bd5f6 Manual merge for fctrl.sv, fpu.S, and ifu.S files 2023-04-03 01:55:23 -07:00
Sydeny
17d41b4d52 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-03 01:54:27 -07:00
Sydney Riley
55655157ae expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions. 2023-04-02 23:51:34 -07:00
Kevin Kim
b38d34b925 Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup 2023-04-02 21:14:35 -07:00
Kevin Kim
8252706691 removed comparator flag to ALU 2023-04-02 21:14:31 -07:00
Kevin Kim
238e97d379 signal renaming on bitmanip alu and alu 2023-04-02 18:42:41 -07:00
Kevin Kim
f175f7e927 changed signal names on clmul and zbc to match book 2023-04-02 18:28:09 -07:00
David Harris
db542543cb Coverage improvement: ieu, hazard, priv 2023-03-31 08:34:34 -07:00
David Harris
fd0c9e973d Coverage improvements in ieu, hazard units 2023-03-31 08:33:46 -07:00
Marcus Mellor
fd08ff2e60 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-31 10:29:10 -05:00
Mike Thompson
9abfef7c39 Merge pull request #179 from davidharrishmc/dev
Fixed broken regression: privileged tests and build root
2023-03-31 10:56:27 -04:00
Marcus Mellor
219176db9b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-31 09:54:02 -05:00
Marcus Mellor
09b2cd304f Address comments in openhwgroup/cvw#180 2023-03-31 09:51:33 -05:00
Kevin Kim
2c6359b097 only pass in relevant comparator flag to ALU 2023-03-30 19:15:33 -07:00
Kevin Kim
1e88ec7eac Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup 2023-03-30 19:04:41 -07:00
Kevin Kim
27a5c9c5d6 Merge branch 'openhwgroup:main' into bitmanip_cleanup 2023-03-30 19:04:36 -07:00
Marcus Mellor
3afd963a9e Disable coverage for branches tested in fpu.s 2023-03-30 19:44:55 -05:00
David Harris
da53f240d3 Refactored InstrValidNotFlushed into CSR Write signals 2023-03-30 17:06:09 -07:00
David Harris
406bb22b6a Started factoring out InstrValidNotFlushed from CSRs 2023-03-30 14:56:19 -07:00
David Harris
f34218666a fctrl updated and buildroot working again 2023-03-30 13:17:15 -07:00
David Harris
9129c3ac22 fctrl continued cleanup 2023-03-30 13:07:39 -07:00
David Harris
01c5d58a64 fctrl continued cleanup 2023-03-30 13:05:56 -07:00
David Harris
b2a102ce79 Started to clean up fctrl 2023-03-30 12:57:14 -07:00
Alec Vercruysse
4b58bb55f2 Make entire cache write path conditional on READ_ONLY_CACHE 2023-03-30 10:32:40 -07:00
Kip Macsai-Goren
3805cf993a unnecessary comments cleanup 2023-03-29 19:32:57 -07:00
Kip Macsai-Goren
491ef14b71 Resolved ImperasDV receiving incorrect cause values 2023-03-29 15:04:56 -07:00
Alec Vercruysse
d507f85190 icache coverage improvements by simplifying logic 2023-03-29 13:04:00 -07:00
David Harris
9d8f9e4428 Reduced number of bits in mcause and medeleg registers 2023-03-29 07:02:09 -07:00
David Harris
59f825a54b Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-29 06:19:10 -07:00
David Harris
f2c24b869d Simplified fctrl 2023-03-28 21:13:48 -07:00
Alec Vercruysse
46df428e56 add check for legal funct3 for IW instructions 2023-03-28 15:59:48 -07:00
David Harris
92a7e86942 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-28 14:33:18 -07:00
Ross Thompson
d0f8db7939 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-28 16:31:50 -05:00