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811 Commits

Author SHA1 Message Date
David Harris
bfa35d727b Fixed redundant check of SupportedFmt on fmv that caused coverage problem on fctrl 2023-04-29 05:58:40 -07:00
David Harris
d5c350c597 Merged coverage exclusions for PMP 2023-04-28 08:04:25 -07:00
David Harris
ca5a71bbe5 PMA Checker coverage 2023-04-28 07:53:59 -07:00
David Harris
22e4f82a99 Commenting 2023-04-28 07:52:08 -07:00
David Harris
f6f43e826a Removed clear from TLBLRU because there is no need to flush LRU state and it causes coverage issues 2023-04-28 07:03:46 -07:00
Ross Thompson
253344f491 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-27 16:38:36 -05:00
David Harris
e962e95e53 CSR code cleanup 2023-04-27 14:12:57 -07:00
David Harris
e519eaa33f Renamed byteUnit to byteop 2023-04-27 14:10:46 -07:00
Ross Thompson
8eaa4bf075 Fixed bug in cacheLRU when NUMWAYS = 2. 2023-04-27 14:30:01 -05:00
Liam
6803347a49 Pmpadrdecs test cases changing AdrMode to 2 or 3 
Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
 2023-04-27 12:23:35 -07:00
David Harris
e69ebc45c0 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-27 07:30:07 -07:00
Alexa Wright
667c54c129
Merge branch 'openhwgroup:main' into main 2023-04-26 16:26:30 -07:00
Alexa Wright
79031e3de0 Added better comment for the exclusion in privdec.sv 2023-04-26 16:25:55 -07:00
David Harris
7c1a4e5e32 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-26 15:40:11 -07:00
David Harris
0ad5165795
Merge pull request #283 from SydRiley/main 
Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
 2023-04-26 15:40:01 -07:00
Sydeny
4595c22fe1 Addressing Redundant logic around BadNanBox, fpu coverage from 96.61% to 96.77% 2023-04-26 14:35:43 -07:00
David Harris
d71d84b386 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-26 05:53:42 -07:00
Alec Vercruysse
6299c0ef0b Cacheway Exclude FlushStage=1 when SetValidWay=1 
We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).

My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
 2023-04-25 20:30:46 -07:00
Alexa Wright
55a74fd315 Excluded and added coverage for WFI test case. 2023-04-25 17:06:57 -07:00
Alec Vercruysse
2f49ee18fe Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign 
FlushWay is always 1 for one way, but by default it is only 1 for
way 0.

The logic that advances FlushWay to ways 1, 2, and 3 only does so
on a subset of conditions that SelFlush is high (in cachefsm), so
this is unreachable for cachways 1-3.
 2023-04-25 17:02:53 -07:00
David Harris
03448aa691 Commented about Sstvecd trap vector alignment 2023-04-24 12:20:33 -07:00
David Harris
8bf9329815 Added M suffix in atomic 2023-04-24 12:19:56 -07:00
Ross Thompson
89a242d143 Might actually have a correct implementation of local history branch prediction. 2023-04-24 13:05:28 -05:00
Ross Thompson
7588de5a36 Fixed the local branch predictor so that it at least compiles. 2023-04-24 11:06:53 -05:00
Diego Herrera Vicioso
c681789296 Excluded coverage for impossible cases in wficountreg and status.MPRV 2023-04-24 02:06:53 -07:00
David Harris
1d532dfcfc Fault on writes to odd-numbered PMPCFG in RV64 2023-04-22 15:32:39 -07:00
David Harris
a5b80bc440 Removed unproven fdivsqrt exclusion 2023-04-22 15:27:05 -07:00
David Harris
8be5ed9b67 Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
David Harris
0871bbe8f2 Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right 2023-04-22 10:07:48 -07:00
David Harris
e11212598f fdivsqrt cleanup 2023-04-20 17:35:01 -07:00
David Harris
f9ca280e01 continued cleanup 2023-04-20 16:48:23 -07:00
David Harris
ea7c50e0ee Reordered fdivsqrtpreproc to follow logic 2023-04-20 16:38:47 -07:00
David Harris
ca0269c094 Started fdivsqrtpreproc flow organization 2023-04-20 16:25:19 -07:00
David Harris
c431278fe6 Fmv h/q comments in controller 2023-04-20 16:24:58 -07:00
David Harris
94d1533264
Merge pull request #256 from cturek/main 
Simplifying fds to follow diagram
 2023-04-20 16:07:22 -07:00
David Harris
24e60c232d
Merge pull request #262 from SydRiley/main 
removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
 2023-04-19 14:49:50 -07:00
Sydeny
b76ed145e6 removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98% 2023-04-19 13:30:12 -07:00
Alec Vercruysse
7ba2bfd4b6 CacheFSM logic simplification for AMO operations 
Ran this by Ross.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
b52512b1ae D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Cedar Turek
30bd1e2a33 created fdivsqrtcycles, moved cycles calculation from FSM to preproc 2023-04-18 16:14:45 -07:00
Cedar Turek
871d495ca1 gave integer bits to D instead of adding manually everywhere 2023-04-18 15:41:04 -07:00
Cedar Turek
054c8d638c moved D flop to preproc 2023-04-18 15:14:17 -07:00
Sydeny
4748fa0f6b Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-17 13:51:16 -07:00
David Harris
bdd5f5e611
Merge pull request #251 from masonadams25/main 
Removed redundent expression to increase coverage
 2023-04-17 12:37:27 -07:00
Mason Adams
4468086e06
Removed redundent expression to increase coverage 2023-04-17 14:13:26 -05:00
David Harris
b00b8ba366 merged coverage exclusions 2023-04-17 10:17:48 -07:00
Diego Herrera Vicioso
34dd481f93 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc 2023-04-15 23:13:39 -07:00
Sydeny
af51b6f16c trimming comments on fctrl bug fixes 2023-04-15 00:48:32 -07:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3 
Full I$ coverage
 2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
Limnanthes Serafini
5952a4b0a3 Final small fix 2023-04-14 14:15:52 -07:00
Limnanthes Serafini
34aedc4f79 indent fix 2023-04-14 14:14:34 -07:00
Limnanthes Serafini
95223bf11c More cleanup 2023-04-13 21:34:50 -07:00
Limnanthes Serafini
28dd41291a More cleanup 2023-04-13 21:02:30 -07:00
Limnanthes Serafini
94b686fcf6 More changes 2023-04-13 21:02:15 -07:00
Limnanthes Serafini
5d12afa671 Some cleanup 2023-04-13 21:01:57 -07:00
David Harris
cfca584bc7 Merged coverage-exclusions 2023-04-13 18:15:23 -07:00
David Harris
b378001213
Merge pull request #237 from SydRiley/main 
fctrl coverage at 100% after removing redundancies from conditionals
 2023-04-13 17:10:46 -07:00
Limnanthes Serafini
e33721fbe4 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
c427b4c896 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
David Harris
8db317133c Starting fdivsqrt cleanup 2023-04-13 16:53:33 -07:00
Sydeny
1dab409bae Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Alec Vercruysse
a52eb01407 Merge branch 'main' into coverage3 2023-04-12 16:00:15 -07:00
Alec Vercruysse
a3d9e11b0f cachefsm exclude icache logic without code reuse 2023-04-12 15:57:45 -07:00
Alec Vercruysse
800f0245f3 Cachefsm gate LRUWriteEn with ~FlushStage 2023-04-12 13:32:36 -07:00
Sydeny
e2520c8a27 fctrl coverage at 100% after removing redundancies from conditional statements 2023-04-12 13:07:30 -07:00
Ross Thompson
f54868f19d
Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
Alec Vercruysse
e303d99d5b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
David Harris
44023e7ee7 Removed unnecessary start term from initialization muxes to simplify and improve coverage 2023-04-12 03:34:01 -07:00
David Harris
28c02a7e6a Fixed fdivsqrt to avoid going from done to busy without going through idle first 2023-04-12 02:48:40 -07:00
Limnanthes Serafini
e0d27ff5a0
Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
d60e3aaf53 only assign ClearDirtyWay for read-write caches 2023-04-12 01:15:35 -07:00
Alec Vercruysse
729f81a0df refactor cachefsm to get full coverage 
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
1ce2ab5daa Coverage and readability improvements to LRUUpdate logic 
The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
214abc7006 Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE 
Some address options are only used in the D$ case.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
6dce58125b Remove FlushStage Logic from CacheLRU 
For coverage.

LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.

Update cache.sv to reflect cacheLRU edit.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
3fc6bb0c40 Exclude (FlushStage & SetValidWay) condition for RO caches 
Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.

I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
 2023-04-12 01:15:35 -07:00
Limnanthes Serafini
fdb81e44c9 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Alexa Wright
34fd402f23 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
Ross Thompson
132016f131 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-09 12:19:44 -05:00
Kevin Thomas
640310cf94 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
David Harris
4a2f641348 Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00
David Harris
495f2ed274 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
David Harris
5119222c2f Commented WFI non-flush in writeback stage of hazard unit 2023-04-07 21:27:13 -07:00
David Harris
7ad8d7f774 Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
David Harris
c24e81c57f Division cleanup 2023-04-06 21:42:34 -07:00
David Harris
ce931d1fc5 Simplified integer division preprocessing in fdivsqrt 2023-04-06 16:43:28 -07:00
David Harris
1569bfbb98 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Jacob Pease
2b9e5608a4 Build doesn't work. AXI Crossbar has problems. 2023-04-06 16:01:58 -05:00
Ross Thompson
fe922c8fac Fixed syntax error. 2023-04-06 15:10:55 -05:00
Ross Thompson
270b3371f1 Added note about strange vivado behavior not inferring block ram. 2023-04-06 15:09:35 -05:00
Ross Thompson
d121364997 Similifed the no byte write enabled version of the sram model. 2023-04-06 14:18:41 -05:00
Kevin Thomas
1931859c45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-06 12:38:41 -05:00
David Harris
52dcd63d1e
Merge pull request #211 from ross144/main 
Fixes the issue introduced by the fix for issue 203
 2023-04-05 21:50:32 -07:00
Ross Thompson
1478115faf Fixed wally64/32priv test hangup. 
The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
 2023-04-05 23:13:45 -05:00
Kevin Thomas
e70a081924 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 17:43:43 -05:00
Ross Thompson
f2c26ff886
Merge pull request #206 from AlecVercruysse/coverage2 
i$ coverage improvements
 2023-04-05 17:29:35 -05:00
Alec Vercruysse
2a3d9f8c89 Update ram1p1rwe (ce & we) coverage exlusion explanation 2023-04-05 14:54:58 -07:00
Kevin Thomas
c4a9bb4269 Formating white space 2023-04-05 15:30:55 -05:00
Kevin Thomas
7345927cb1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 15:04:12 -05:00
Ross Thompson
d1ac175e27 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 14:55:12 -05:00
Alec Vercruysse
61e19c2ddf Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE 
To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
d3a988c96c make Cache Flush Logic dependent on !READ_ONLY_CACHE 
read-only caches do not have flush logic since they do not have to
deal with dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
247af17b6b remove ClearValid from cache 
The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
3867142f10 change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe 
the byte write-enables were always tied high, so we can use
RAM without byte-enable to increase coverage.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
4993b1b426 turn off ce coverage for ram1p1rwe 
According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.

For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.

Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
277f507e9a add ram1p1rwe for read-only cache ways (remove byte-enable) 
- increases coverage
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
c0206cfcb3 fix typo in cachway setValid input comment 2023-04-05 11:48:18 -07:00
Alec Vercruysse
270200bc1c put cacheLRU coverage explanation on another line 
the `: explanation` syntax was not working
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
c41f4d2e7b Exclude CacheLRU log2 function from coverage 2023-04-05 11:48:18 -07:00
Ross Thompson
7c2512446c Progress on bug 203. 2023-04-05 13:20:04 -05:00
Kevin Thomas
5e5842893b Minor change with the IFU in the decompress module, in the compressed instruction truth table. 
The truth table is already fully covered, removed redundant last case checking
 2023-04-05 10:27:52 -05:00
David Harris
b7b1f2443f Fixed WFI to commit when an interrupt occurs 2023-04-04 09:32:26 -07:00
Ross Thompson
c21a5aaaf7
Merge pull request #194 from davidharrishmc/dev 
Bit manipulation support in ImperasDV.  Test improvements.
 2023-04-04 09:13:27 -05:00
Kevin Kim
d7deed1690
Merge branch 'openhwgroup:main' into zbc_optimize 2023-04-03 23:45:49 -07:00
Kevin Kim
ce8a401a84 reduced mux3 to mux2 for input signal to clmul 2023-04-03 22:53:46 -07:00
David Harris
57ee9f3a5a Merged priv.S edits 2023-04-03 18:07:14 -07:00
Sydeny
8cfd221444 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-03 13:41:55 -07:00
Ross Thompson
91803dc684
Merge pull request #178 from AlecVercruysse/coverage 
Improve I$ coverage by simplifying logic
 2023-04-03 14:22:46 -05:00
David Harris
af8f1ab786 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-03 06:13:16 -07:00
Sydeny
7e5e9d928e Manual merge for fctrl.sv, fpu.S, and ifu.S files 2023-04-03 01:55:23 -07:00
Sydeny
58eed1bba2 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-03 01:54:27 -07:00
Sydney Riley
440e41bb3e expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions. 2023-04-02 23:51:34 -07:00
Kevin Kim
03bf8f373f Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup 2023-04-02 21:14:35 -07:00
Kevin Kim
5e7bbeddd1 removed comparator flag to ALU 2023-04-02 21:14:31 -07:00
Kevin Kim
f35b287e66 signal renaming on bitmanip alu and alu 2023-04-02 18:42:41 -07:00
Kevin Kim
9a4fa6ce96 changed signal names on clmul and zbc to match book 2023-04-02 18:28:09 -07:00
David Harris
03b4f6660c Coverage improvement: ieu, hazard, priv 2023-03-31 08:34:34 -07:00
David Harris
b95730e3a1 Coverage improvements in ieu, hazard units 2023-03-31 08:33:46 -07:00
Marcus Mellor
984d4b9918 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-31 10:29:10 -05:00
Mike Thompson
a28a457099
Merge pull request #179 from davidharrishmc/dev 
Fixed broken regression: privileged tests and build root
 2023-03-31 10:56:27 -04:00
Marcus Mellor
c7ec42eaab Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-31 09:54:02 -05:00
Marcus Mellor
913cdecb65 Address comments in openhwgroup/cvw#180 2023-03-31 09:51:33 -05:00
Kevin Kim
97181e063b only pass in relevant comparator flag to ALU 2023-03-30 19:15:33 -07:00
Kevin Kim
bd1ac13f5f Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup 2023-03-30 19:04:41 -07:00
Kevin Kim
b43e4d8d0d
Merge branch 'openhwgroup:main' into bitmanip_cleanup 2023-03-30 19:04:36 -07:00
Marcus Mellor
64f15d48de Disable coverage for branches tested in fpu.s 2023-03-30 19:44:55 -05:00
David Harris
77d5f1c81b Refactored InstrValidNotFlushed into CSR Write signals 2023-03-30 17:06:09 -07:00
David Harris
25cd1cc432 Started factoring out InstrValidNotFlushed from CSRs 2023-03-30 14:56:19 -07:00
David Harris
a4ae1b9cbb fctrl updated and buildroot working again 2023-03-30 13:17:15 -07:00
David Harris
fc01f45c80 fctrl continued cleanup 2023-03-30 13:07:39 -07:00
David Harris
e68e473da9 fctrl continued cleanup 2023-03-30 13:05:56 -07:00
David Harris
b07c71ea41 Started to clean up fctrl 2023-03-30 12:57:14 -07:00
Alec Vercruysse
132074523f Make entire cache write path conditional on READ_ONLY_CACHE 2023-03-30 10:32:40 -07:00
Kip Macsai-Goren
94f03b0d78 unnecessary comments cleanup 2023-03-29 19:32:57 -07:00
Kip Macsai-Goren
da905b4eb9 Resolved ImperasDV receiving incorrect cause values 2023-03-29 15:04:56 -07:00
Alec Vercruysse
dac011c1d2 icache coverage improvements by simplifying logic 2023-03-29 13:04:00 -07:00
David Harris
de2a0da9e9 Reduced number of bits in mcause and medeleg registers 2023-03-29 07:02:09 -07:00
David Harris
96e3c3bea8 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-29 06:19:10 -07:00
David Harris
043e4fe5f4 Simplified fctrl 2023-03-28 21:13:48 -07:00
Alec Vercruysse
bfb4f0d6eb add check for legal funct3 for IW instructions 2023-03-28 15:59:48 -07:00
David Harris
77affa7ccd Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-28 14:33:18 -07:00
Ross Thompson
73e6972f0b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-28 16:31:50 -05:00
David Harris
5e352bf72e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-28 14:27:08 -07:00
Ross Thompson
69f6b291c6 Possible fix for issue 148. 
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.

I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.

This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
 2023-03-28 14:47:08 -05:00
Kevin Kim
adabb7c236 comment formatting 2023-03-28 11:40:19 -07:00
Kevin Kim
4c9670a082
Merge branch 'openhwgroup:main' into bitmanip_cleanup 2023-03-28 11:31:18 -07:00
David Harris
f0cab709f2 Added support (untested) for half and quad conversions 2023-03-28 10:53:06 -07:00
David Harris
40311c4f62 fixed fp->fp conversions 2023-03-28 10:35:41 -07:00
David Harris
e5955c5dd8 support more fp -> fp conversions 2023-03-28 10:28:01 -07:00
David Harris
fd2d08f501 Fixed fmv decoder 2023-03-28 10:21:33 -07:00
Ross Thompson
d55b0c8c1f
Merge pull request #169 from davidharrishmc/dev 
PMP Fix to issue 132
 2023-03-28 11:49:00 -05:00
David Harris
aa31b45d88 Fixed RV32 tests after PMP fix 2023-03-28 08:35:23 -07:00
David Harris
39d3bf8e8a Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests 2023-03-28 06:58:17 -07:00
David Harris
20ebf7e536 CSRS privileged coverage test 2023-03-28 04:37:56 -07:00
Ross Thompson
8504774a11 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-27 11:55:19 -05:00
David Harris
edaa306240 Removed unnecessary monitor 2023-03-27 09:52:38 -07:00
Ross Thompson
88c572d9bb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-27 10:22:48 -05:00
Lee Moore
39ac6be103
Merge branch 'openhwgroup:main' into add-linux 2023-03-27 09:44:13 +01:00
Kevin Kim
f3edbcea15 removed unnecessary signal indices 2023-03-26 20:06:55 -07:00
Kevin Kim
b4d6021b3b removed unneccesary input signal from zbb 2023-03-26 19:39:49 -07:00
Ross Thompson
3fc0c4b34e Modified plic and uart to remove async reset. This removes vivado critical warning. 2023-03-24 20:37:48 -05:00
Ross Thompson
78ab9f59af Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
Ross Thompson
1f37e6dcea Renamed controllerinputstage to controllerinput to match book. 2023-03-24 17:57:02 -05:00
David Harris
0dc6f9b991 Merged ross's spacing fixes 2023-03-24 15:47:26 -07:00
David Harris
46e0841011
Merge pull request #159 from ross144/main 
Renamed signal to match book
 2023-03-24 15:34:59 -07:00
Ross Thompson
730f3ac84e Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
Jacob Pease
303c997a69 Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore 2023-03-24 17:01:27 -05:00
Ross Thompson
0511c73e22 Replaced tabs -> spaces cache. 2023-03-24 15:15:38 -05:00
Ross Thompson
1ff15c3882 Updated EBU to replace tabs with spaces. 2023-03-24 15:01:38 -05:00
Kevin Kim
eb8fe3ed17 Zero/Sign extend mux in Shifter, Zero extend mux in Bitmanip alu 2023-03-24 11:52:51 -07:00
David Harris
a5e569245b Shifter capitalization 2023-03-24 09:01:07 -07:00
Ross Thompson
2956c11dbc Renamed ebu signal. 2023-03-24 10:51:04 -05:00
David Harris
9f1c1958a6 Query about CondExtA 2023-03-24 08:35:33 -07:00
David Harris
34e0b3bc61 Shifter sign simplification and capitalization 2023-03-24 08:27:30 -07:00
David Harris
25a1ea7d23 FPU detect illegal instructions 2023-03-24 08:12:32 -07:00
David Harris
59f948d47c Start of EBU coverage tests 2023-03-24 08:12:02 -07:00
David Harris
d04f4cedf6 ALUControl Elimination 2023-03-24 08:10:48 -07:00
David Harris
ac0b669518 Merged ALUOp into ALUControl to simplify ALU mux 2023-03-24 07:28:42 -07:00
David Harris
9ffac8315b Simplified rotate source to shifter 2023-03-24 06:49:26 -07:00
David Harris
c6561fffd4 BMU simplifications 2023-03-24 06:18:06 -07:00
David Harris
e67b077a3e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-24 05:59:48 -07:00
Kevin Kim
3ec4b23ff5 minor formatting 2023-03-23 22:28:21 -07:00
Kevin Kim
f07397df76 comments 2023-03-23 22:22:25 -07:00
Kevin Kim
125cb0ce44 removed redundant signals 
-fixed some comments too
 2023-03-23 22:20:37 -07:00
Kevin Kim
969b2723ef bitmanip alu submodule passes lint and regression 2023-03-23 21:56:03 -07:00
Kevin Kim
e2a5c87b73 more progress. Failing regression 2023-03-23 20:42:49 -07:00
Kevin Kim
1eb04d9747
Merge branch 'openhwgroup:main' into bitmanip-alu 2023-03-23 19:53:50 -07:00
David Harris
dc156cc09c Removed unnecessary XZero from fdivsqrt 2023-03-23 17:25:59 -07:00
David Harris
7e947023c1 Merged BMU 2023-03-23 17:24:40 -07:00
Kevin Kim
f9fc30e1cb fixed rori rv32 bug 2023-03-23 16:06:46 -07:00
Kevin Kim
7b1567829c more progress on bitmanip alu modularization 2023-03-23 16:02:38 -07:00
David Harris
f8ad1b3db8 Improved IEU and bitmanip test coverage 2023-03-23 14:24:41 -07:00
Kevin Kim
e5be0bd2fd started bitmanip alu modularization 2023-03-23 14:02:28 -07:00
David Harris
99c471ccfe Added csrwrites.S test case for privileged tests 2023-03-23 10:55:32 -07:00
Kevin Kim
bfaf646ed2 Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip 2023-03-22 10:34:19 -07:00
Kevin Kim
cd50018087 remove outdated 2023-03-22 10:34:17 -07:00
Kevin Kim
605f41cd55
Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 10:33:15 -07:00
Kevin Kim
b3fbdba7f3 updated header comments to indicate chapter 15 2023-03-22 10:31:21 -07:00
Kevin Kim
c197a040c8 remove helper python script 2023-03-22 10:27:59 -07:00
Kevin Kim
b9b8023674 formatting 2023-03-22 10:26:04 -07:00
Kevin Kim
bc2bbc0529 min/max mux optimize 2023-03-22 10:25:54 -07:00
Kevin Kim
80a490888a formatting 2023-03-22 10:14:12 -07:00
eroom1966
1c3c8be148 support linux 2023-03-22 17:10:32 +00:00
David Harris
c4c7f5378e Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault 2023-03-22 06:29:30 -07:00
David Harris
32c54db595 Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0 2023-03-22 04:41:57 -07:00
David Harris
77fb1b57f4 Fix Issue 145 2023-03-22 04:33:14 -07:00
Kevin Kim
2e149f9a31 Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-21 11:20:05 -07:00
David Harris
376bbcc71d Renamed intdivrestoring to div 2023-03-21 05:51:02 -07:00
David Harris
0fd385e5de Renamed intdivrestoring to div 2023-03-20 16:22:06 -07:00
Kevin Kim
73fbc21aab formatting 2023-03-20 14:25:05 -07:00
Kevin Kim
37b73ea42e more structural mux changes 2023-03-20 14:23:54 -07:00
Kevin Kim
7a6d1ab393 added bitmanip 64 tests to updated regression script 
+ alu structural mux changes
 2023-03-20 14:19:39 -07:00
Kevin Kim
728be29ce3 formatting 2023-03-20 13:09:49 -07:00
Kevin Kim
07a43e1935 Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-20 13:06:10 -07:00
David Harris
0ecde4ab4f formatting cleanup 2023-03-20 12:45:10 -07:00
Kevin Kim
9e5360e31f format + min/max structural mux 2023-03-20 09:37:57 -07:00
David Harris
471305bda0 Eliminate transitions to FLUSH and WRITEBACK in cachefsm for READ_ONLY_CACHE 2023-03-19 10:41:47 -07:00
David Harris
835381a122 Removed flq from LLEN=64 2023-03-19 10:25:04 -07:00
David Harris
02e7e7d011 Added comments about PMP checker fixes when test cases will be ready to initialize PMP before entering user mode 2023-03-19 05:46:34 -07:00
David Harris
031cc6967a Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression. 2023-03-18 10:10:58 -07:00
David Harris
70e4c71f41 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-18 09:24:37 -07:00
David Harris
08ce265420 Replaced FenceM with InvalidateICacheM for event counting of fence.i 2023-03-18 09:24:31 -07:00
Ross Thompson
407b3c488d Book updates. 2023-03-14 13:09:50 -05:00
Ross Thompson
a27051b8a8 Updated NextAdr to NextSet. 2023-03-13 14:54:13 -05:00
Ross Thompson
cb019f9aed Updated CAdr to CacheSet. 2023-03-13 14:53:00 -05:00
Ross Thompson
ede9d49ce4 Changes BTA to BPBTA. 2023-03-12 14:36:46 -05:00
Ross Thompson
e233b63752 Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10. 2023-03-12 13:21:22 -05:00
Kevin Kim
bc9cd4a26e more checks in bitmanip decode 2023-03-10 17:17:24 -08:00
Kevin Kim
869c7283e8 formatting 2023-03-10 14:32:01 -08:00
Kevin Kim
827cf567e6 removed redundant convinvb signal 2023-03-10 14:18:24 -08:00
Kevin Kim
a5841c6fb2 removed redundant condinvb mux 2023-03-10 14:17:38 -08:00
David Harris
ed22433916 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-10 12:47:30 -08:00
David Harris
2614448218 Simplified SLT and SLTU code in ALU 2023-03-09 15:14:52 -08:00
Kevin Kim
6ee15c6e2c more comprehensive illegal b instr. check 2023-03-09 12:44:51 -08:00
Kevin Kim
5853854f52 fixed bmu bug 
- accidentally deleted count instruction decode
 2023-03-09 12:35:42 -08:00
Ross Thompson
fa8a550e12 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-09 13:29:38 -06:00
Kevin Kim
ba13f6794e Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip 2023-03-08 16:22:47 -08:00
Kevin Kim
2175702f6d cleaner bmu decode logic 2023-03-08 16:22:43 -08:00
Ross Thompson
6d2d7d181e Updated testbench to record coremark performance counters. 
Added comment about mtval probably not being correct for compressed instructions.
 2023-03-08 17:11:27 -06:00
kipmacsaigoren
10e0935207
Merge branch 'openhwgroup:main' into bit-manip 2023-03-07 21:29:03 -08:00
David Harris
ec0873ff16 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-07 14:49:23 -08:00
Kevin Kim
f2090d25c4
Merge branch 'bit-manip' into illegal_specific 2023-03-07 14:07:59 -08:00
Kevin Kim
8eb4eb2100
Merge branch 'openhwgroup:main' into illegal_specific 2023-03-07 14:06:22 -08:00
Kevin Kim
20af58cdd4 alu formatting 2023-03-07 14:01:47 -08:00
Kevin Kim
b33b0afc77 specifc instruction handling for B's 
- Added BALUSrcBD, BaseALUSrcB for distinguishing between base instruction I/IW and Bitmanip instruction I/IW
 2023-03-07 13:58:08 -08:00
kipmacsaigoren
01f78835cb
Merge branch 'openhwgroup:main' into priv-tests 2023-03-07 13:46:55 -08:00
Kip Macsai-Goren
1ceaaad592 Merge remote-tracking branch 'upstream/main' into bit-manip 2023-03-07 13:45:04 -08:00
Kip Macsai-Goren
47bbe72d1f Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip 2023-03-07 13:44:51 -08:00
Kip Macsai-Goren
34c0f86d37 Merge branch 'main' of github.com:kipmacsaigoren/cvw into bit-manip 2023-03-07 13:44:19 -08:00
Kevin Kim
3b874b964f Merge remote-tracking branch 'origin' into illegal_specific 2023-03-07 11:30:36 -08:00
Kevin Kim
dc456415c1 formatting 2023-03-07 10:57:52 -08:00
Kevin Kim
7ec33ca094 shifter sign generation logic optimize 2023-03-07 10:57:06 -08:00
David Harris
dce6d33531 editorconfig to specify tabs/spaces. Fixed some tabs. Turn off coverage to speed up simulation 2023-03-07 06:31:40 -08:00
Kevin Kim
7651d41c90 reverted backing to working version 2023-03-07 00:29:58 -08:00
Kevin Kim
8c20d67659 reverted to working version 2023-03-07 00:28:07 -08:00
Ross Thompson
17f80285ca Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-06 22:29:27 -06:00
Ross Thompson
b8dca927f2 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-06 18:39:15 -06:00
Ross Thompson
4b539de184 Renamed signals to be consistent with textbook. 2023-03-06 18:29:31 -06:00
Ross Thompson
6fc157e628 Renamed PCFSpill to PCSpillF. 2023-03-06 17:50:57 -06:00
Ross Thompson
e831efddaf Renamed InstrFirstHalf to InstrFirstHalfF. 2023-03-06 17:48:57 -06:00
Ross Thompson
82ada79b11 Renamed ebuarbfsm to ebufsmarb to match figures. 2023-03-06 17:47:55 -06:00
David Harris
4fd461e520 Fixed bug about rv64 shifts only using 6 bits of funct7 2023-03-06 13:10:51 -08:00
David Harris
94dd39795e Simplified decoder default to illegal instruction 2023-03-06 11:21:11 -08:00
David Harris
08f1ed8e53 More detailed decoding of load/store/branch/jump 2023-03-06 11:15:48 -08:00
David Harris
a01e0bd318 Improved decoding illegal instructions in controller 2023-03-06 11:02:42 -08:00
Kevin Kim
4a31ab1bc3 structural changes in cnt.sv 2023-03-06 06:44:15 -08:00
Kevin Kim
45697f050d formatting 2023-03-06 06:20:25 -08:00
Kevin Kim
c38a5d9151 formatting 
- reverted back to ALUResult signal in alu.sv
 2023-03-06 06:19:01 -08:00
Kevin Kim
474b69967a formatted files 2023-03-06 05:52:08 -08:00
Kevin Kim
288c7ad48c updated license header 2023-03-06 05:41:53 -08:00
Kevin Kim
cec1e89c78 bug fix 2023-03-05 15:20:48 -08:00
Kevin Kim
19beed7866 extend unit structural mux 2023-03-05 15:09:02 -08:00
Kevin Kim
7531bf1fd6 zbb result select mux structural 2023-03-05 14:57:30 -08:00
Kevin Kim
3656d42ac0 zbc input mux structural 2023-03-05 14:26:31 -08:00
Kevin Kim
869e812aa8 revA signals to cnt, zbb 2023-03-05 14:26:24 -08:00
Kevin Kim
0e6ea0ee60 ALU changes 
- added PreShiftAmt signal for shadd
- condinvB now muxes from B instead of mask
 2023-03-05 14:06:24 -08:00
Kevin Kim
3d5ee8d964 bug in bctrl 
- deleted the min/minu decoding for some reason.
 2023-03-04 23:56:33 -08:00
Kevin Kim
6ead150cb1 BSelect from OH encoding to Binary 2023-03-04 23:19:31 -08:00
Kevin Kim
4b1ee5a196 alu pre-shift 
-changed ALU pre shift logic to use a 2 bit shifter instead of mux
 2023-03-04 23:07:06 -08:00
Kevin Kim
b0f152de28 added python script 
-I've been using this python script to make quick changes to the bitmanip controller
 2023-03-04 22:54:32 -08:00
Kevin Kim
499c3c5c30 Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip 2023-03-04 22:44:09 -08:00
Kevin Kim
6295178073 removed rotate signal in datapath and instead packed into the new BALUControl Signal 
- BALUControl contains Rotate, Mask, PreShift signals to select from the respective generation muxes in the ALU
 2023-03-04 22:44:03 -08:00
Kip Macsai-Goren
0ba1a59a70 added reset values to stime and stimecmp registers 2023-03-04 15:06:15 -08:00
Kip Macsai-Goren
e76e7120c0 Merge remote-tracking branch 'upstream/main' into bit-manip 2023-03-04 14:43:12 -08:00
Kevin Kim
b6dd855395 zbc result mux is now structural 2023-03-04 09:22:21 -08:00
Kevin Kim
6e52113208 Rotate signal now gets generated in bmu ctrl 2023-03-03 22:57:49 -08:00
Kevin Kim
18ab538a5e license comments 2023-03-03 21:52:34 -08:00
Kevin Kim
efce306aab removed redundant signals in controller 2023-03-03 21:52:25 -08:00
Kevin Kim
448e950eba b controller generates comparison signed flag and controller branch signed logic updated accordingly 2023-03-03 17:12:29 -08:00