Commit Graph

811 Commits

Author SHA1 Message Date
Ross Thompson
284ff0ab0b Fixed minor performance bug with CBOZ. 2023-08-24 17:08:20 -05:00
Ross Thompson
fbcf6be06d Now have CBOZ instructions working! 2023-08-24 16:47:35 -05:00
Ross Thompson
e8bc339638 Oups there was a bug in the SATP fix. RV32GC was broken by the changes. 2023-08-23 09:42:46 -05:00
Ross Thompson
d9a001e87a Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-08-23 09:15:13 -05:00
Jacob Pease
0f29587b0b Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP. 2023-08-22 16:25:56 -05:00
Ross Thompson
a899be7deb Fixed bug with the cbo.inval clearing already cleared lines. 2023-08-21 17:51:51 -05:00
Ross Thompson
6337aab757 Fixed issue when with flush miss. 2023-08-18 16:36:13 -05:00
Ross Thompson
e3bb0d2820 Now we have invalidate, clean, and flush working. 2023-08-18 16:32:22 -05:00
Ross Thompson
b9af790b81 Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests. 2023-08-18 15:59:39 -05:00
Ross Thompson
b842fdb863 Might have working cbo clean and flush instructions. 2023-08-18 14:48:21 -05:00
Ross Thompson
8c7eafffad Fixed cbo instruction decode. 2023-08-18 11:32:30 -05:00
Ross Thompson
a14966e516 Updated the hazard logic for CMO operations. 2023-08-17 17:58:49 -05:00
Ross Thompson
bfde4d2c78 Found first bug in CMO implementation. 2023-08-17 16:57:54 -05:00
Ross Thompson
6a8a82d9e8 CMOZ now implemented in the D cache. 2023-08-17 12:46:40 -05:00
Ross Thompson
e74e4f3a60 Added clean and flush to cache fsm. 2023-08-16 14:23:56 -05:00
Ross Thompson
b5ca41fd2a More progress towards cmo. 2023-08-15 18:17:15 -05:00
Ross Thompson
6284773733 The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush. 2023-08-14 16:39:18 -05:00
Ross Thompson
f678133d19 Initial CMO implementation. Just adds control signals into the L1 caches. 2023-08-14 15:43:12 -05:00
Ross Thompson
3e66653f37 Cache cleanup. 2023-07-31 14:12:53 -05:00
Ross Thompson
141e90d425
Merge pull request #372 from davidharrishmc/dev
PLIC part select warnings fixed
2023-07-31 11:28:28 -04:00
David Harris
55d4f28efe
Merge pull request #373 from harshinisrinath1001/main
Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
2023-07-30 22:46:44 -07:00
Harshini Srinath
01fc7c5284
Fixed formatting 2023-07-30 18:36:25 -07:00
Harshini Srinath
811e2fd94c
Fixed formatting 2023-07-30 18:30:23 -07:00
Harshini Srinath
01bbddc5da
Fixed formatting 2023-07-30 18:27:22 -07:00
Harshini Srinath
a697c89a2a
Fixed formatting 2023-07-30 18:18:24 -07:00
Harshini Srinath
1bc1a68210
Fixed formatting 2023-07-30 18:06:25 -07:00
Harshini Srinath
86164acc84
Fixed formatting 2023-07-30 18:00:39 -07:00
Harshini Srinath
6b5aa47f23
Fixed formatting 2023-07-30 17:54:47 -07:00
Harshini Srinath
8c7ea5a47a
Fixed formatting 2023-07-30 17:46:23 -07:00
Harshini Srinath
69711503a8
Fixed formatting 2023-07-30 17:39:37 -07:00
Harshini Srinath
70599d3153
Fixed formatting 2023-07-30 17:38:22 -07:00
Harshini Srinath
2846a2f567
Fixed spacing 2023-07-30 17:32:46 -07:00
Harshini Srinath
fffde4ef7d
Fixed spacing 2023-07-30 17:22:40 -07:00
Harshini Srinath
31c09cf3cf
Fixed spacing 2023-07-30 17:21:52 -07:00
Harshini Srinath
c49944a495
Fixed spacing 2023-07-30 17:21:22 -07:00
Harshini Srinath
84d72bc203
Fixed spacing 2023-07-30 17:18:25 -07:00
Harshini Srinath
b8570c4bef
Fixed spacing 2023-07-30 16:59:27 -07:00
Harshini Srinath
872f9ed9cc
Fixed spacing 2023-07-30 16:57:57 -07:00
David Harris
f7f4c5fa7b renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
David Harris
388d699baa Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
54d6a1afa2 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Ross Thompson
8d88ef93bc Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Ross Thompson
52dc71507f Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Ross Thompson
1b8edacd8d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
David Harris
0cfb5c7b3a Formatting cleanup 2023-07-25 05:11:38 -07:00
Ross Thompson
717833b11a Removed all old references to the old flash card controller.
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
6099b0e763 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
0063665baf Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now. 2023-07-21 16:31:26 -05:00
Ross Thompson
37078f3d9b Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00