Ross Thompson
619bbd9d83
Merge branch 'bp' into main
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Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Teo Ene
b50faef94d
Updated coremark .do file for easier debugging
2021-03-03 15:10:39 -06:00
Teo Ene
d02e22feac
Updated coremark .do file for easier debugging
2021-03-02 17:23:39 -06:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
Teo Ene
8491deb1a9
Changed .do file back to run all
2021-02-25 09:58:54 -06:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
Ross Thompson
c856003f73
RAS needs to be reset or preloaded. For now I just reset it.
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Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6
Added FlushF to hazard unit.
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Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
06e975ac2f
minor change to wave file.
2021-02-19 09:08:13 -06:00
Ross Thompson
7d6093b302
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
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About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Ross Thompson
8cbc9f7e51
Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables.
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Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-17 22:20:28 -06:00
Ross Thompson
bbe0db3ebe
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
bbracker
deb7780897
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Teo Ene
5f84ed407c
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
David Harris
842c374de9
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
Jarred Allen
088fbbcbf0
Change busybear test to use work-busybear library
2021-02-03 11:12:47 -05:00
Jarred Allen
e5bd749e2a
Refactor regression test
2021-02-02 17:22:29 -05:00
Noah Boorstin
d2064987e9
Add busybear testbench to nightly regression checking
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If you don't like how I did this please feel free to undo it
2021-02-02 22:05:35 +00:00
Jarred Allen
da43b2be53
Fix intermittent errors caused by weird library stuff
2021-02-02 11:20:09 -05:00
Jarred Allen
f143518b23
Fix issues in parallel regression testing
2021-02-01 23:29:03 -05:00
Noah Boorstin
d592db79c9
busybear: change register file checking to only store register changed
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this should make parsedRegs.txt much smaller
2021-02-02 01:27:43 +00:00
Jarred Allen
5cf3d188c6
Parallelize regression-wally.p
2021-02-01 15:40:27 -05:00
Noah Boorstin
a82f8977c6
busybear: NOP out floating point instructions for now
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Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
2021-01-30 19:52:47 +00:00
Noah Boorstin
cca60ed06d
update busybear testbench to conform to new structure
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aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
David Harris
9511dcac84
Connected AHB bus to Uncore
2021-01-29 23:43:48 -05:00
David Harris
6d5b01357d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 15:38:01 -05:00
David Harris
d104e5a4be
Moving data memory to uncore
2021-01-29 15:37:51 -05:00
Noah Boorstin
7183910c84
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
Noah Boorstin
84e4193db6
busybear testbench: test on first 100k instrs
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currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
2021-01-29 00:14:23 -05:00
Noah Boorstin
c4964352f0
busybear: simulate first 10k instructions
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I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
2021-01-28 19:44:58 -05:00
Noah Boorstin
96ceac0e80
busybear: fix misaligned writing checking
2021-01-28 19:35:09 -05:00
Noah Boorstin
df1d174aea
busybear: add more test instructions
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currently testing first 1k instrs
2021-01-28 16:41:37 -05:00
Noah Boorstin
cbab07967a
more of the same fixes
2021-01-28 16:26:15 -05:00
Noah Boorstin
03cea6e29b
more misaligned read fixing
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I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
2021-01-28 16:14:35 -05:00
Noah Boorstin
e65166bec5
busybear testbench: understand bytemask for writes
2021-01-28 15:42:47 -05:00
Noah Boorstin
9a45b49536
busybear: ret is only 1 word
2021-01-28 14:47:40 -05:00
Noah Boorstin
5a5237b908
add speculative exception for compressed instructions
2021-01-28 14:40:35 -05:00
Noah Boorstin
632fecf43a
testbench now understands lw not aligned to 8 bytes
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also busybear now has first 500 instead of 100 instrs
and prints current instrs less
2021-01-28 13:33:22 -05:00
Noah Boorstin
be3d024527
Busybear test now processes first 100 instrs correctly!
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- changed test parser to recognize lw in addition to lw
also, added temporary questa files (wlft*) to .gitignore
2021-01-28 01:19:27 -05:00
Noah Boorstin
ed85fda42a
fix memory write address decoding for busybear tests
2021-01-28 01:19:26 -05:00
Noah Boorstin
840528a05f
update busybear testbench to conform to new structure
2021-01-27 23:42:19 -05:00
David Harris
9d821aab0f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-27 22:49:55 -05:00
David Harris
37a58cea17
Repartitioned with Instruction Fetch Unit, Integer Execution Unit
2021-01-27 22:49:47 -05:00
Noah Boorstin
74e57a8472
update busybear testbench to conform to new structure
2021-01-27 12:54:09 -05:00
David Harris
092edf953e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-27 06:40:39 -05:00
