David Harris
bc70f0b933
Merge pull request #869 from jordancarlin/installation
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Installation and setup overhaul
2024-08-08 15:39:23 -07:00
David Harris
77b45f2d75
Fix creating cvw-arch-verif work directory
2024-08-08 05:25:28 -07:00
Jordan Carlin
76eef03fe4
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-08-07 20:22:55 -07:00
Huda-10xe
0303314f4e
Adding RVVI Functional Coverage Support
2024-08-07 14:31:16 +05:00
Jordan Carlin
42a9bbf28d
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-25 21:21:57 -07:00
Rose Thompson
94a1ce32e7
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 17:48:34 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
David Harris
040b359813
Added more RV64I coverage generation
2024-07-22 08:52:19 -07:00
David Harris
e949c9cfba
Removed more obsolete imperas scripts
2024-07-21 19:47:23 -07:00
David Harris
7fd8c6e29a
Removed outdated wally-imperas files
2024-07-21 19:45:22 -07:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Jordan Carlin
8853fd52bc
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-18 21:36:00 -07:00
Rose Thompson
19e9dc5ce0
Fixed wally.do to correctly log functional coverage.
2024-07-16 15:52:52 -05:00
David Harris
d86ef9673d
More attempts at functional coverage
2024-07-15 15:34:44 -07:00
David Harris
ac05fa5553
Attempt at functional coverage; breaks code and functional coverage
2024-07-15 14:20:48 -07:00
David Harris
467436e30c
Renamed --coverage to --ccov and moved UCDB files to questa/ucdb
2024-07-15 05:32:16 -07:00
Jordan Carlin
09a061b580
Merge remote-tracking branch 'upstream/main' into installation
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Fix derivgen.pl shebang conflict
2024-07-08 06:46:41 -07:00
David Harris
12717a65f2
Fixed location of imperas.ic with new misa_B_Zba_Zbb_Zbs
2024-07-04 12:29:59 -07:00
David Harris
775930ae4f
Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test
2024-07-04 07:36:56 -07:00
Jordan Carlin
a30d4b29df
Additional shebang updates
2024-07-03 21:34:48 -07:00
Ross Thompson
2d8973df1d
Updated wavefile to use new names.
2024-06-19 13:57:28 -07:00
Ross Thompson
64712d2243
Updated wave to match changes in testbench.
2024-06-19 13:51:50 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Rose Thompson
a88d5f403b
Functional coverage works with wally.do
2024-05-28 14:02:54 -05:00
Rose Thompson
0c5b70c40a
It's a bit hacky. But I've got functional coverage working with our wally.do script and testbench.sv.
2024-05-28 13:54:48 -05:00
Rose Thompson
48fd365b9d
Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage.
2024-05-28 13:00:17 -05:00
Rose Thompson
4a1e856b18
Almost working functional coverage in wally.do
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riscvISACOV is now loading, but for some reason I still cannot get it to record anything.
Instead it is just logging the instructions.
2024-05-27 18:15:12 -05:00
Rose Thompson
92ee56c1a1
Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV.
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testbench.sv was missing the trace2cov instance.
2024-05-27 17:25:20 -05:00
Rose Thompson
4c0261fd2c
Closer. Needed to reorder includes and defines.
2024-05-27 15:37:16 -05:00
Rose Thompson
ff611016c7
Closer?
2024-05-27 14:11:02 -05:00
Rose Thompson
2985cfb7eb
Preliminary work to merge functional coverage into wally.do.
2024-05-27 11:59:13 -05:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
bf9f45d319
We have a simulation of the ethernet transmission working.
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This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
Rose Thompson
b127c19242
Merge branch 'main' into rvvi
2024-05-20 16:31:06 -05:00
Rose Thompson
a885240fbd
temporary commit to help debug merging testbench.sv with testbench-imperas.sv
2024-05-17 12:36:00 -05:00
Rose Thompson
bd8450734b
Fixed more bugs with wally.do.
2024-05-17 10:39:00 -05:00
Rose Thompson
46e6459965
Updated script to run linux with imperasDV.
2024-05-14 13:46:27 -05:00
Rose Thompson
970af9551c
Fixed bug with gui mode testbench_fp
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removed old wally-linux-imperas.do
2024-05-14 13:41:20 -05:00
Rose Thompson
30bea18dec
Maybe have imperasDV linux simulation merged into wally.do
2024-05-14 12:38:19 -05:00
Rose Thompson
e8f5545076
Got imperasDV running linux simulation again.
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Now need to merge do files.
2024-05-13 16:43:13 -05:00
Rose Thompson
ceb31fec68
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
93ea5b0c1e
Fixed wavefile to have function logger.
2024-05-10 08:50:42 -05:00
David Harris
04457d49f7
Updated sim-testfloat-verilator to use wsim
2024-05-10 05:03:24 -07:00
David Harris
37fc45cd35
Updated Questa wally.do to terminate on a compile error
2024-05-06 11:28:00 -07:00
David Harris
1274ec55af
Resolved merge conflict
2024-04-26 16:15:23 -07:00
Quswar Abid
f999ccadf4
/cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch
2024-04-26 15:55:39 -07:00
David Harris
5d97858806
Moved functional coverage files to sim/questa and to tests/riscvdv
2024-04-24 11:46:38 -07:00
Quswar Abid
7b441d2881
Bringup of RISCV-DV to collect functional coverage - Update to track RV64IMAFDC_Zicsr related coverpoints from riscvISACOV
2024-04-23 18:20:29 -07:00
