1605 Commits

Author	SHA1	Message	Date
David Harris	5e961973cb	IEU lint cleanup	2021-10-23 10:51:53 -07:00
David Harris	708b914a65	Lint cleanup from wallypipeliendhart	2021-10-23 10:29:52 -07:00
David Harris	817795f619	Lint cleanup: ahblite, ifu, hart	2021-10-23 10:12:33 -07:00
David Harris	2abec36221	Lint cleanup	2021-10-23 09:58:52 -07:00
David Harris	6ae9aa7d80	lint cleanup: FPU and privileged	2021-10-23 09:41:24 -07:00
David Harris	80d2b9bc0d	subword read and csrc lint cleanup	2021-10-23 09:29:15 -07:00
David Harris	0eabd0ecc2	FMA and CSRC lint cleanup	2021-10-23 09:20:24 -07:00
David Harris	5235e61d9e	Lint cleanup	2021-10-23 09:06:21 -07:00
David Harris	bf3eb7b814	update scripts for handling src/*/* subdirectories	2021-10-23 08:54:29 -07:00
David Harris	7732d38c36	lint cleaning and moved files into subdirectories	2021-10-23 08:53:32 -07:00
David Harris	ff409d4fe7	Lint cleanup	2021-10-23 08:39:21 -07:00
David Harris	8b854bb1c2	Cleaned up LINT erors	2021-10-23 06:28:49 -07:00
David Harris	5142bfd624	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-23 06:15:49 -07:00
David Harris	3407b63c8a	Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.	2021-10-23 06:15:26 -07:00
kipmacsaigoren	c2f4b49b15	removed reduntant definitions for FPU in MISA.	2021-10-22 15:18:25 -05:00
James E. Stine	a60e19dc3f	Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking	2021-10-22 13:41:50 -05:00
Katherine Parry	00cc1e0c5c	put the FMA priority encoders into their own module	2021-10-22 10:03:12 -07:00
James E. Stine	0e0a107a98	Get rid of lint warning - still need more testing though	2021-10-21 15:19:22 -05:00
James E. Stine	49721a169b	Clean up some FPU and add pipelined fpdivsqrt to fpu.sv	2021-10-21 13:52:12 -05:00
James E. Stine	129ef03b2d	Fix fpdivsqrt lint error on CPA for convergence	2021-10-20 17:46:13 -05:00
David Harris	687703f0d8	removed .* from wallypipeliendsoc	2021-10-20 13:49:18 -07:00
James E. Stine	7536e0a2ee	Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.	2021-10-20 12:00:41 -05:00
David Harris	4aeadaacf0	moved coemark and testsBP to tests	2021-10-20 09:10:06 -07:00
David Harris	0e4f6392d6	Move tests into subdirectory and moved wavedrom out of project	2021-10-20 09:03:21 -07:00
David Harris	8747791bb8	radix 2 SRT checkin	2021-10-19 14:08:16 -07:00
James E. Stine	ed179b0bd9	Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this	2021-10-19 12:09:43 -05:00
James E. Stine	b65a4bd040	Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).	2021-10-19 11:58:06 -05:00
David Harris	8d08ca6a1e	Changed some flops to settable	2021-10-18 17:05:29 -07:00
David Harris	df0b65e483	replaced flopenl with flopenr when clearing to 0	2021-10-18 16:53:18 -07:00
David Harris	d0b9ebd2ef	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-18 15:44:31 -07:00
David Harris	47f7a5db9c	Fixed multiplier and pointed arch tests to new path in addins	2021-10-18 15:43:59 -07:00
Ross Thompson	d8d414665c	fixed issues with dc shell not liking modules with parameters without default values.	2021-10-18 17:24:15 -05:00
James E. Stine	d895fd7ee5	Sanitization some more on mult_cs.sv	2021-10-18 05:24:16 -05:00
James E. Stine	aafa988ca2	Update some on mult_cs and delete DW02_mult.v	2021-10-18 05:06:49 -05:00
James E. Stine	5a1835622c	Add hacky hand-made carry/save multiplier - will improve	2021-10-16 10:37:29 -05:00
Katherine Parry	33e5a078bf	cvtfp module documented	2021-10-14 15:25:31 -07:00
James E. Stine	6b30adb309	Clean up some signals - beautification onging	2021-10-14 17:12:00 -05:00
Kip Macsai-Goren	ffcf5f5825	Fixed typo in imperas64mmu tests causing PMP tests not to run.	2021-10-14 13:42:24 -07:00
Skylar Litz	395e070917	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-13 15:38:32 -07:00
Skylar Litz	d639222519	add StallM signal back to DivStartE control	2021-10-13 15:34:40 -07:00
James E. Stine	eb64a7f0c9	Update to fpdivsqrt to go on posedge as it should. Also an update to ... individual regression test for TestFloat (still needs some tweaking)	2021-10-13 17:14:42 -05:00
bbracker	886a650da4	change infrastructure to expect only 6.3 million from buildroot	2021-10-12 10:41:15 -07:00
Shreya Sanghai	d783acbbc5	added DESIGN_COMPLIER to forgotten config files	2021-10-12 10:14:04 -07:00
Katherine Parry	09f51871c5	lint warnings fixed	2021-10-12 09:45:02 -07:00
Katherine Parry	4ea56ac68b	some fpu lint warnings fixed - still working on it	2021-10-11 18:32:03 -07:00
Shreya Sanghai	51185478df	made redunantmul generate DW02_multp for synopsys sythnesis	2021-10-11 11:54:39 -07:00
Shreya Sanghai	295a3c7af2	actually added redundant mul	2021-10-11 11:29:13 -07:00
David Harris	f9b37c3ce1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-11 11:21:39 -07:00
David Harris	062fbfb610	Extended lint to check rv32/64g (including fpu. Not clean yet.	2021-10-11 11:20:42 -07:00
Shreya Sanghai	324230e2f9	added redundant multiplier	2021-10-11 11:20:12 -07:00